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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i 145 Revision 1.4 (08-19-08)
DATASHEET
10.2.3 Microwire EEPROM
Based on the configuration strap eeprom_type_strap, various sized Microwire EEPROMs are
supported. The varying size ranges are supported by additional bits in the address field
(EPC_ADDRESS) of the EEPROM Command Register (E2P_CMD). Within each size range, the
largest EEPROM uses all the address bits, while the smaller EEPROMs treat the upper address bits
as don’t cares. The EEPROM controller drives all the address bits as requested regardless of the
actual size of the EEPROM. The supported size ranges for Microwire operation are shown in
Table 10.3.
Refer to Section 15.5.10, "Microwire Timing," on page 454 for detailed Microwire timing information.
10.2.3.1 Microwire Master Commands
Table 10.4, Table 10.5 , and Table 10.6 detail the Microwire command set, including the number of clock
cycles required, for 7, 9, and 11 address bits respectively. These commands are detailed in the
following sections as well as in Section 14.2.4.1, "EEPROM Command Register (E2P_CMD)," on
page 198.
Table 10.3 Microwire EEPROM Size Ranges
eeprom_size_strap[1:0] # OF ADDRESS BITS EEPROM SIZE EEPROM TYPES
00 7 128 x 8 93xx46A
01 9 256 x 8 and 512 x 8 93xx56A, 93xx66A
10 11 1024 x 8 and 2048 x 8 93xx76A, 93xx86A
11 RESERVED
Table 10.4 Microwire Command Set for 7 Address Bits
INST
START
BIT OPCODE ADDRESS
DATA TO
EEPROM
DATA FROM
EEPROM
# OF
CLOCKS
ERASE 1 11 A6 A5 A4 A3 A2 A1 A0 - (RDY/~BSY) 10
ERAL 1 00 1 0 X X X X X - (RDY/~BSY) 10
EWDS 1 00 0 0 X X X X X - Hi-Z 10
EWEN 1 00 1 1 X X X X X - Hi-Z 10
READ 1 10 A6 A5 A4 A3 A2 A1 A0 - D7 - D0 18
WRITE 1 01 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/~BSY) 18
WRAL 1 00 0 1 X X X X X D7 - D0 (RDY/~BSY) 18
Table 10.5 Microwire Command Set for 9 Address Bits
INST
START
BIT OPCODE ADDRESS
DATA TO
EEPROM
DATA FROM
EEPROM
# OF
CLOCKS
ERASE 1 11 A8 A7 A6 A5 A4 A3 A2 A1 A0 - (RDY/~BSY) 12
ERAL 1 00 1 0 X X X X X X X - (RDY/~BSY) 12