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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i 31 Revision 1.4 (08-19-08)
DATASHEET
Note: Refer to Chapter 8, "Host Bus Interface (HBI)," on page 99 for additional information regarding
the use of these signals.
60
Data FIFO
Direct Access
Select
FIFO_SEL IS Data FIFO Direct Access Select: When driven
high, all accesses to the LAN9311/LAN9311i are
directed to the RX and TX Data FIFO’s. All reads
are from the RX Data FIFO, and all writes are to
the TX Data FIFO. In this mode, the address input
is ignored. Refer to Section 14.1.3, "Direct FIFO
Access Mode," on page 168 for additional
information.
61
Endianess
Select
END_SEL IS Endianess Select: When this signal is set high,
big endian mode is selected. When low, little
endian mode is selected. This signal may be
dynamically changed or held static. Refer to
Chapter 8, "Host Bus Interface (HBI)," on page 99
for additional information.
Table 3.5 EEPROM Pins
PIN NAME SYMBOL
BUFFER
TYPE DESCRIPTION
96
EEPROM
Microwire
Data Input
EEDI IS
(PD)
EEPROM Microwire Data Input (EEDI): In
Microwire EEPROM mode (EEPROM_TYPE = 0),
this pin is the Microwire EEPROM serial data input.
EEPROM I
2
C
Serial Data
Input/Output
EE_SDA IS/OD8 EEPROM I
2
C Serial Data Input/Output
(EE_SDA): In I
2
C EEPROM mode
(EEPROM_TYPE = 1), this pin is the I
2
C EEPROM
serial data input/output.
98
EEPROM
Microwire
Data Output
EEDO O8 EEPROM Microwire Data Output: In Microwire
EEPROM mode (EEPROM_TYPE
= 0), this pin is
the Microwire EEPROM serial data output.
Note: In I
2
C mode (EEPROM_TYPE=1), this pin
is not used and is driven low.
EEPROM
Type Strap
EEPROM_TYPE
IS
Note 3.3
EEPROM Type Strap: Configures the EEPROM
type. See Note 3.4
0 = Microwire Mode
1 = I
2
C Mode
99
EEPROM
Microwire
Serial Clock
EECLK O8 EEPROM Microwire Serial Clock (EECLK): In
Microwire EEPROM mode (EEPROM_TYPE
= 0),
this pin is the Microwire EEPROM clock output.
EEPROM I
2
C
Serial Clock
EE_SCL IS/OD8 EEPROM I
2
C Serial Clock (EE_SCL): In I
2
C
EEPROM mode (EEPROM_TYPE=1), this pin is
the I
2
C EEPROM clock input/open-drain output.
EEPROM
Size Strap 1
EEPROM_SIZE_1
IS
Note 3.5
EEPROM Size Strap 1: Configures the high bit of
the EEPROM size range as specified in Section
10.2, "I2C/Microwire Master EEPROM Controller,"
on page 138. This bit is not used for I
2
C
EEPROMs. See Note 3.4.
Table 3.4 Host Bus Interface Pins (continued)
PIN NAME SYMBOL
BUFFER
TYPE DESCRIPTION