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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Revision 1.4 (08-19-08) 452 SMSC LAN9311/LAN9311i
DATASHEET
15.5.8 PIO Write Cycle Timing
Please refer to Section 8.5.8, "PIO Writes," on page 111 for a functional description of this mode.
Note: A PIO write cycle begins when both nCS and nWR are asserted. The cycle ends when either
or both nCS and nWR are de-asserted. These signals may be asserted and de-asserted in any
order.
Figure 15.8 PIO Write Cycle Timing
Table 15.12 PIO Write Cycle Timing Values
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
cycle
Write Cycle Time 45 nS
t
csl
nCS, nWR Assertion Time 32 nS
t
csh
nCS, nWR De-assertion Time 13 nS
t
asu
Address Setup to nCS, nWR Assertion 0 nS
t
ah
Address Hold Time 0 nS
t
dsu
Data Setup to nCS, nWR De-assertion 7 nS
t
dh
Data Hold Time 0 nS
t
ah
A[x:1], END_SEL
nCS, nWR
D[15:0]
t
asu
t
csl
t
cycle
t
csh
t
dh
t
dsu