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TDM Interface: Front Panel I/O
PmT1 and PmE1 User’s Manual 10002367-02
6-8
Table 6-7: MDI Bit Field Format
FRONT PANEL I/O
Connectors P1 and P2 provide the TDM signals for the PmT1 and PmE1 front panel I/O con-
figurations. The manufacturer part number for this eight-pin connector is Stewart Connec-
tor Systems SS-610808-NF-P-5.
Figure 6-3: Front Panel I/O Connectors, P1 and P2
Field: Width: Function
1
:
1. These are read-only bits. You must enable, disable, or clear interrupts at the DS2153/DS2151 framer
chip itself. The SR1 status register on each framer chip corresponds to bits 5 and 7. Similarly, the SR2
status register on each framer chip corresponds to bits 4 and 6.
Start 2 The “01” transition frames the beginning of an MDI cycle.
The MDI Interface is reset when the MDIO line (which is pulled up) is
high for greater than 40 clocks.
OpCode 3 000
2
Reserved
001
2
Reserved
010
2
Module ID Register Read (returns 02
16
)
011
2
Module Interrupt Register Read
1
Bits 0—3undefined
Bit 4INT1—, from DS2153/DS2151 Channel 1
Bit 5INT2—, from DS2153/DS2151 Channel 1
Bit 6INT1—, from DS2153/DS2151 Channel 0
Bit 7INT2—, from DS2153/DS2151 Channel 0
100
2
DS2153/DS2151 Channel 0 (TDMA) Register Write
101
2
DS2153/DS2151 Channel 1 (TDMB) Register Write
110
2
DS2153/DS2151 Channel 0 (TDMA) Register Read
111
2
DS2153/DS2151 Channel 1 (TDMB) Register Read
Address 8 Address of a T1 or E1 controller register (determined by 2153 or 2151
interface controller) For ID register and interrupt register cycles the
address field is ignored.
Data 8 Register Read/Write Data On read cycles the MDI protocol requires
that the accessing application continue to clock the interface while
waiting for the MDIO line to be driven low. Once low the following 8
bits will be valid data.
P2
(TDMA - Channel 0)
P1
(TDMB - Channel 1)
Pin 1