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PMC/PCI Interface: PMC Connector Pin Assignments
10002367-02 PmT1 and PmE1 User’s Manual
7-11
LOCK*: LOCK sustained tri-state signal indicates that an atomic operation may require multiple
transactions to complete.
PAR: PARITY is even parity across AD00-AD31 and C/BE0-C/BE3*. Parity generation is required by
all PCI agents. This tri-state signal is stable and valid one clock after the address phase, and
one clock after the bus master indicates that it is ready to complete the data phase (either
IRDY* or TRDY* is asserted). Once PAR is asserted, it remains valid until one clock after the
completion of the current data phase.
PERR*: PARITY ERROR sustained tri-state line is used to report parity errors during all PCI transac-
tions.
REQ*: REQUEST output pin indicates to the arbiter that a particular master wants to use the bus.
RST*: RESET assertion of this input line brings PCI registers, sequencers, and signals to a consis-
tent state.
SERR*: SYSTEMS ERROR open-collector output signal is used to report any system error with cata-
strophic results.
STOP*: STOP sustained tri-state signal is used by the current target to request that the bus master
stop the current transaction.
TRDY*: TARGET READY sustained tri-state signal indicates the target’s ability to complete the cur-
rent data phase of the transaction.