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Each physical CPU core contains logic to support two physical threads. This results in up to eight
physical threads, or the equivalent of 8 logical CPUs, when two processor modules are installed
and enabled in rx3600 servers. The operating system kernel attaches one or more software
processes to each available thread. In multiple processor servers, having more threads means
all software processes are launched and executed faster.)
Itanium Processor Load Order
For a minimally loaded server, one Itanium processor module must be installed in CPU socket
0 on the processor board CRU, and its threads must be enabled by user actions. You can install
an additional identical processor in CPU socket 1.
Processor Module Behaviors
All enabled CPUs and their threads become functional when the system powers on. Each thread
acquires instructions from the CPU instruction and data caches to complete early self tests and
rendezvous.
The CPU communicates with the PDH until memory is configured. After the memory is
configured, the CPUs communicate with memory.
Local machine check abort (MCA) events cause the physical CPU core and one or both of its
logical CPUs within that processor module to fail while all other physical CPUs and their logical
threads continue operating. Double-bit data cache errors in any physical CPU core cause a Global
MCA event that causes all logical threads and physical CPUs in the server to fail and reboot the
operating system.
Processor Problem Identification
• A diagnostic LED only lights for physical CPU core errors, when a specific processor module
is isolated. If there is any uncertainty about a specific CPU the CRU LED on the diagnostic
panel is not lighted. Check the SEL for any errors or warnings.
• For physical configuration errors, for example, when there is no processor module installed
in CPU socket 0, all the CRU LEDs on the diagnostic LED panel light for all the missing
processor modules.
• No diagnostic messages are reported for single-bit errors that are corrected in both instruction
and data caches during corrected machine check (CMC) events to physical CPU core.
Diagnostic messages are reported for CMC events when thresholds are exceeded for single-bit
errors. Fatal processor errors cause global and local MCA events.
Table 5-15 and Table 5-16 list the processor events that light and that may light the diagnostic
panel LEDs.
Table 5-15 Processor Events that Light Diagnostic Panel LEDs
NotesSourceCauseIPMI EventDiagnostic
LEDs
This event follows
other failed
processors.
SFWThe processor failed and
was deconfigured.
Type E0h, 39d:04d
BOOT_DEConFIG_CPU
Processors
Threshold
exceeded for cache
parity errors on the
processor.
WIN
Agent
Too many cache errors were
detected by the processor.
Type E0h, 5823d:26d
PFM_CACHE_ERR_PROC
Processors
Threshold
exceeded for cache
errors from the
processor,
corrected by Zx2.
WIN
Agent
Too many corrected errors
detected by the platform.
Type E0h, 5824d:26d
PFM_CORR_ERROR_MEM
Processors
CPU, Memory and SBA 159