Filter
Top Products
the ioconfig mps_optimize [on|off] command from a non-PCIe system, the following
output will be displayed:
-------------
Shell> ioconfig mps_optimize
ioconfig: PCIe MPS optimization is not supported.
Shell> ioconfig mps_optimize on
ioconfig: PCIe MPS optimization is not supported.
Exit status code: Unsupported
Shell>
-----------------
To restore MPS to the default values use the default clear command. See “default” (page 327).
Processor
The server processor subsystem accommodates one or two dual-core Itanium® processor modules.
The processor subsystem consists of the following elements:
• zx2 CEC front side bus, memory, and I/O controller
• System clock generation and distribution
• Circuitry for manageability and fault detection
The zx2 CEC and the processor modules are located on the processor board assembly. Each
processor connects to the processor board through a zero insertion force (ZIF) socket. The processor
board is mounted on a removable carrier tray that is attached to the processor board access door.
Access the assembly through the front of the server after the memory carrier is removed.
Memory
The server DIMMS are seated on memory boards that are enclosed in an extractable memory
carrier assembly. The memory boards plug directly into sockets on the processor board when
the memory carrier assembly is fully seated.
Table 1-3 lists the two types of supported memory carriers and the memory configurations of
each carrier.
Table 1-3 Supported Memory Configurations
Maximum Memory
Configuration
Minimum Memory
Configuration
Memory Boards InstalledMemory Carrier Type
32-GB (eight 4-GB DIMMs)2-GB (one pair: two 1-GB
DIMMs)
Two 4-DIMM memory
boards
8-DIMM memory carrier
(standard)
96-GB (24x4-GB DIMMs)2-GB (one quad: four
512-MB DIMMs)
Two 12-DIMM memory
boards
24-DIMM memory carrier
(optional, high-capacity)
The server supports the following DIMM sizes:
• 512-MB
• 1-GB
• 2-GB
• 4-GB
Figure 1-3 is a block diagram of the 8-DIMM memory carrier that shows data, addresses, and
controls that flow through the CEC and to and from the processors.
Server Subsystems 29