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Version 1.10 12/01/02 12-1
12
Protocols-PCIBusSupport
12.1 PCI Root Bridge I/O Support
These sections (Sections 12.1 and 12.2) describe the PCI Root Bridge I/O Protocol. This protocol
provides an I/O abstraction for a PCI Root Bridge that is produced by a PCI Host Bus Controller.
A PCI Host Bus Controller is a hardware component that allows access to a group of PCI devices
that share a common pool of PCI I/O and PCI Memory resources. This protocol is used by a PCI
Bus Driver to perform PCI Memory, PCI I/O, and PCI Configuration cycles on a PCI Bus. It also
provides services to perform different types of bus mastering DMA on a PCI bus. PCI device
drivers will not directly use this protocol. Instead, they will use the I/O abstraction produced by the
PCI Bus Driver. Only drivers that require direct access to the entire PCI bus should use this
protocol. In particular, functions for managing PCI buses are defined here although other bus types
may be supported in a similar fashion as extensions to this specification.
All the services described in this chapter that generate PCI transactions follow the ordering rules
defined in the PCI Specification. If the processor is performing a combination of PCI transactions
and system memory transactions, then there is no guarantee that the system memory transactions
will be strongly ordered with respect to the PCI transactions. If strong ordering is required, then
processor-specific mechanisms may be required to guarantee strong ordering. For example,
Itanium-based systems may require the use of memory fences to guarantee ordering.
12.1.1 PCI Root Bridge I/O Overview
The interfaces provided in the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL are for performing
basic operations to memory, I/O, and PCI configuration space. The system provides abstracted
access to basic system resources to allow a driver to have a programmatic method to access these
basic system resources.
The EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL allows for future innovation of the platform. It
abstracts device-specific code from the system memory map. This allows system designers to make
changes to the system memory map without impacting platform independent code that is
consuming basic system resources.