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Extensible Firmware Interface Specification
2-22 12/01/02 Version 1.10
A platform can be viewed as a set of processors and a set of core chipset components that may
produce one or more host buses. Figure 2-9 shows a platform with n processors (CPUs), and a set
of core chipset components that produce m host bridges.
OM13150
Core Chipset Components
. . .
. . .
CPU 2
CPU
n
Front Side Bus
CPU 1
HB 2
HB
m
HB 1
Figure 2-9. Host Bus Controllers
Each host bridge is represented in EFI as a device handle that contains a Device Path Protocol
instance, and a protocol instance that abstracts the I/O operations that the host bus can perform.
For example, a PCI Host Bus Controller supports one or more PCI Root Bridges that are abstracted
by the PCI Root Bridge I/O Protocol. Figure 2-10 shows an example device handle for a PCI
Root Bridge.
O
M
15221
Device Handle
EFI_DEVICE_PATH_PROTOCOL
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
Figure 2-10. PCI Root Bridge Device Handle