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Protocols — PCI Bus Support
Version 1.10 12/01/02 12-55
12.4 EFI PCI I/O Protocol
This section provides a detailed description of the EFI_PCI_IO_PROTOCOL. This protocol is
used by code, typically drivers, running in the EFI boot services environment to access memory and
I/O on a PCI controller. In particular, functions for managing devices on PCI buses are defined
here.
The interfaces provided in the EFI_PCI_IO_PROTOCOL are for performing basic operations to
memory, I/O, and PCI configuration space. The system provides abstracted access to basic system
resources to allow a driver to have a programmatic method to access these basic system resources.
The main goal of this protocol is to provide an abstraction that simplifies the writing of device
drivers for PCI devices. This goal is accomplished by providing the following features:
• A driver model that does not require the driver to search the PCI busses for devices to manage.
Instead, drivers are provided the location of the device to manage or have the capability to be
notified when a PCI controller is discovered.
• A device driver model that abstracts the I/O addresses, Memory addresses, and PCI
Configuration addresses from the PCI device driver. Instead, BAR (Base Address Register)
relative addressing is used for I/O and Memory accesses, and device relative addressing is used
for PCI Configuration accesses. The BAR relative addressing is specified in the PCI I/O
services as a BAR index. A PCI controller may contain a combination of 32-bit and 64-bit
BARs. The BAR index represents the logical BAR number in the standard PCI configuration
header starting from the first BAR. The BAR index does not represent an offset into the
standard PCI Configuration Header because those offsets will vary depending on the
combination and order of 32-bit and 64-bit BARs.
• The Device Path for the PCI device can be obtained from the same device handle that the
EFI_PCI_IO_PROTOCOL resides.
• The PCI Segment, PCI Bus Number, PCI Device Number, and PCI Function Number of the
PCI device if they are required. The general idea is to abstract these details away from the PCI
device driver. However, if these details are required, then they are available.
• Details on any nonstandard address decoding that is not covered by the PCI device’s Base
Address Registers.
• Access to the PCI Root Bridge I/O Protocol for the PCI Host Bus for which the PCI device is a
member.
• A copy of the PCI Option ROM if it is present in system memory.
• Functions to perform bus mastering DMA. This includes both packet based DMA and common
buffer DMA.