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IXF1104 4-Port Gigabit Ethernet Media Access Controller
Datasheet 128
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
5.12.1.1 CLK125
The system interface clock, which supplies the clock to the majority of the internal circuitry, is the
125 MHz clock. The source of this clock must meet the following specifications:
• 2.5 V CMOS drive
• +/- 50 ppm
• Maximum duty cycle distortion 40/60
5.12.2 SPI3 Receive and Transmit Clocks
The IXF1104 MAC transmit clock requirements include the following:
• 3.3 V LVTTL drive
• +/- 50 ppm
• Maximum frequency of 133 MHz in MPHY mode
• Maximum frequency of 125 MHz in SPHY mode
• Maximum duty cycle distortion 45/55
The IXF1104 MAC meets the following specifications for the receive clock:
• 3.3 V LVTTL drive
• +/- 50 ppm
• Maximum frequency of 133 MHz in MPHY mode
• Maximum frequency of 125 MHz in SPHY mode
• Maximum duty cycle distortion 45/55
5.12.3 RGMII Clocks
The RGMII interface is governed by the Hewlett-Packard* 1.2a specification. The IXF1104 MAC
compliant to this specification with the following:
• 2.5 V CMOS drive
• Maximum duty cycle distortion 40/60
• +/- 100 ppm
• 125 MHz for 1000 Mbps, 25 MHz for 100 Mbps and 2.5 MHz for 10 Mbps
5.12.4 MDC Clock
The IXF1104 MAC supports the IEEE 802.3 MII Management Interface, also known as the
Management Data Input/Output (MDIO) Interface. The IXF1104 MAC meets the following
specifications for this clock:
• 2.5 V CMOS drive
• 2.5/18 MHz operation (selectable by the MDC speed bit in the “MDIO Control ($0x683)")
• 50/50 duty cycle for 2.5 MHz operation