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IXF1104 4-Port Gigabit Ethernet Media Access Controller
Datasheet 86
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Figure 12. MPHY Receive Logical Timing
Figure 13. MPHY 32-Bit Interface
B0660-02
TFCLK
TENB
TDAT[31:0]
TPRTY
TERR
TSX
TSOP
TEOP
Network Processor
SPI3 Bus
IXF1104 MPHY
Mode
Transceiver
TFCLK
TENB_0
TDAT[31:0]
TPRTY_0
TMOD[1:0]
TMOD[1:0]
RMOD[1:0]
RMOD[1:0]
TERR_0
TSX
TSOP_0
TEOP_0
RFCLK
RENB
RDAT[31:0]
RPRTY
RPRTY
RVAL
RERR
RSX
RSOP
REOP
RPRTY_0
RFCLK
RENB_0
RDAT[31:0]
RVAL_0
RERR_0
RSX
RSOP_0
REOP_0
DTPA_0:3
STPA
PTPA
TADR[1:0]
DTPA_0:3
STPA
PTPA
TADR[1:0]
Transceiver
Transceiver
Transceiver
Line-Side Interface
Port 0
Port 1
Port 3
Port 2