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Datasheet 15
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
39
Modified Section 4.3, “Signal Description Tables” [changed heading from “Signal Naming
Conventions; added new headings Section 4.1.1, “Signal Name Conventions” and Section 4.1.2,
“Register Address Conventions”; and added/enhanced material under headings.
58
Added new Section 4.5, “Multiplexed Ball Connections” with Table 16 “Line Side Interface
Multiplexed Balls” and Table 17 “SPI3 MPHY/SPHY Interface”.
63
Modified Section 4.7, “Power Supply Sequencing” [changed language under this section and added
Section 4.7.1, “Power-Up Sequence” and Section 4.7.2, “Power-Down Sequence”].
63
Modified Table 5 “Power Supply Sequencing” [deleted 3.3 V Supplies Stable; changed Apply 1.8 V
to VDD, AVDD1P8_1, and AVDD1P8_2; changed Apply 2.5 V to AVDD2P5_1 and AVDD2P5_2].
61
Modified Table 18 “Definition of Output and Bi-directional Balls During Hardware Reset” [changed
comments for Optical Modules].
64
Modified Table 20 “Pull-Up/Pull-Down and Unused Ball Guidelines” [changed TRST_L to pull-down;
added MDIO, UPX_RDY_L, I
2
C_DATA_3:0, and TX_DISABLE_3:0].
64
Added new Section 4.9, “Analog Power Filtering” [including Figure 6 “Analog Power Supply Filter
Network” on page 65 and Table 21 “Analog Power Balls” on page 65].
66
Modified/edited text under Section 5.1, “Media Access Controller (MAC)” [rearranged and created
new bullets].
67 Modified first paragraph under Section 5.1.1.1, “Padding of Undersized Frames on Transmit”.
67 Modified entire Section 5.1.1.3, “Filtering of Receive Packets”.
68 Added new Section 5.1.1.3.6, “Filter CRC Error Packets”.
69 Added note under Table 22 “CRC Errored Packets Drop Enable Behavior”.
69
Added new Section 5.1.2, “Flow Control” including Figure 7 “Packet Buffering FIFO”, Figure 8
“Ethernet Frame Format”, and Figure 9 “PAUSE Frame Format”.
73
Replaced Section 5.1.2.1.5, “Transmit Pause Control Interface” [added Table 23 “Valid Decodes for
TXPAUSEADD[2:0]” and modified Table 10 “Transmit Pause Control Interface”.
74 Modified Figure 10 “Transmit Pause Control Interface”
75 Added note under Section 5.1.3.1, “Configuration”.
76 Added table note to Table 24 “Operational Mode Configuration Registers”.
77 Added note under Section 5.1.4.3, “Fiber Forced Mode”.
79 Modified Section 5.1.6.2, “TX Statistics” [added text to third sentence in first paragraph].
79
Modified Section 5.1.6.3, “Loss-less Flow Control” [changed “two kilometers” to “five kilometers” in
last sentence.
80 Modified Section 5.1.7.1.2, “RX FIFO” [changed 10 KB to 9.6 KB; added text to last paragraph].
83 Rewrote/replaced Section 5.2, “SPI3 Interface”.
86 Edited signal names in Figure 13 “MPHY 32-Bit Interface”.
90
Edited signal names in Figure 16 “SPHY Connection for Two Intel
®
IXF1104 MAC Ports (8-Bit
Interface)”.
91
Added new Section 5.2.2.9, “SPI3 Flow Control”.
[Removed old “Packet-Level and Byte-Level Transfers” section.}
94 Modified Figure 17 “MAC GMII Interconnect” [edited signal names].
NA
Removed old Section 5.3.3 Electrical Requirements and Table 27 “Electrical Requirements” –
changed Input high current Max from 40 to 15 and Input low current Min from -600 to -15.
96 Added a note under Section 5.4, “Reduced Gigabit Media Independent Interface (RGMII)”.
96 Modified Figure 18 “RGMII Interface” [edited signal names].
Revision Number: 007
Revision Date: March 24, 2004
(Sheet 2 of 5)
Page # Description