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Contents
Datasheet 5
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
5.6.2.3 Receiver Operational Overview ...........................................................105
5.6.2.4 Selective Power-Down.........................................................................105
5.6.2.5 Receiver Jitter Tolerance.....................................................................105
5.6.2.6 Transmit Jitter ......................................................................................106
5.6.2.7 Receive Jitter .......................................................................................106
5.7 Optical Module Interface...................................................................................................107
5.7.1 Intel® IXF1104 MAC-Supported Optical Module Interface Signals .....................107
5.7.2 Functional Descriptions .......................................................................................108
5.7.2.1 High-Speed Serial Interface.................................................................108
5.7.2.2 Low-Speed Status Signaling Interface.................................................108
5.7.3 I²C Module Configuration Interface......................................................................110
5.7.3.1 I
2
C Control and Data Registers............................................................110
5.7.3.2 I
2
C Read Operation..............................................................................110
5.7.3.3 I
2
C Write Operation..............................................................................111
5.7.3.4 I²C Protocol Specifics...........................................................................112
5.7.3.5 Port Protocol Operation .......................................................................113
5.7.3.6 Clock and Data Transitions..................................................................113
5.8 LED Interface....................................................................................................................115
5.8.1 Modes of Operation .............................................................................................115
5.8.2 LED Interface Signal Description.........................................................................116
5.8.3 Mode 0: Detailed Operation.................................................................................116
5.8.4 Mode 1: Detailed Operation.................................................................................117
5.8.5 Power-On, Reset, Initialization ............................................................................118
5.8.6 LED DATA Decodes............................................................................................118
5.8.6.1 LED Signaling Behavior .......................................................................119
5.9 CPU Interface ...................................................................................................................120
5.9.1 Functional Description .........................................................................................121
5.9.1.1 Read Access........................................................................................121
5.9.1.2 Write Access........................................................................................121
5.9.1.3 CPU Timing Parameters......................................................................122
5.9.2 Endian..................................................................................................................122
5.10 TAP Interface (JTAG) .......................................................................................................123
5.10.1 TAP State Machine..............................................................................................123
5.10.2 Instruction Register and Supported Instructions..................................................124
5.10.3 ID Register...........................................................................................................125
5.10.4 Boundary Scan Register......................................................................................125
5.10.5 Bypass Register...................................................................................................125
5.11 Loopback Modes ..............................................................................................................125
5.11.1 SPI3 Interface Loopback .....................................................................................125
5.11.2 Line Side Interface Loopback ..............................................................................126
5.12 Clocks...............................................................................................................................127
5.12.1 System Interface Reference Clocks.....................................................................127
5.12.1.1 CLK125 ................................................................................................128
5.12.2 SPI3 Receive and Transmit Clocks .....................................................................128
5.12.3 RGMII Clocks.......................................................................................................128
5.12.4 MDC Clock...........................................................................................................128
5.12.5 JTAG Clock..........................................................................................................129
5.12.6 I
2
C Clock..............................................................................................................129
5.12.7 LED Clock............................................................................................................129