Intel IXF1104 Computer Hardware User Manual


 
Contents
6 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
6.0 Applications...............................................................................................................................130
6.1 Change Port Mode Initialization Sequence.......................................................................130
6.2 Disable and Enable Port Sequences................................................................................131
6.2.1 Disable Port Sequence........................................................................................131
6.2.2 Enable Port Sequence.........................................................................................131
7.0 Electrical Specifications...........................................................................................................132
7.1 DC Specifications .............................................................................................................133
7.1.1 Undershoot / Overshoot Specifications ...............................................................135
7.1.2 RGMII Electrical Characteristics..........................................................................135
7.2 SPI3 AC Timing Specifications.........................................................................................137
7.2.1 Receive Interface Timing.....................................................................................137
7.2.2 Transmit Interface Timing....................................................................................139
7.3 RGMII AC Timing Specification........................................................................................141
7.4 GMII AC Timing Specification...........................................................................................142
7.4.1 1000 Base-T Operation .......................................................................................142
7.4.1.1 1000 BASE-T Transmit Interface.........................................................142
7.4.1.2 1000BASE-T Receive Interface...........................................................143
7.5 SerDes AC Timing Specification.......................................................................................144
7.6 MDIO AC Timing Specification.........................................................................................145
7.6.1 MDC High-Speed Operation Timing....................................................................145
7.6.2 MDC Low-Speed Operation Timing.....................................................................145
7.6.3 MDIO AC Timing..................................................................................................146
7.7 Optical Module and I
2
C AC Timing Specification .............................................................147
7.7.1 I
2
C Interface Timing.............................................................................................147
7.8 CPU AC Timing Specification...........................................................................................149
7.8.1 CPU Interface Read Cycle AC Timing.................................................................149
7.8.2 CPU Interface Write Cycle AC Timing.................................................................149
7.9 Transmit Pause Control AC Timing Specification.............................................................151
7.10 JTAG AC Timing Specification .........................................................................................152
7.11 System AC Timing Specification.......................................................................................153
7.12 LED AC Timing Specification............................................................................................154
8.0 Register Set................................................................................................................................155
8.1 Document Structure..........................................................................................................155
8.2 Graphical Representation.................................................................................................155
8.3 Per Port Registers ............................................................................................................156
8.4 Register Map ....................................................................................................................156
8.4.1 MAC Control Registers........................................................................................163
8.4.2 MAC RX Statistics Register Overview.................................................................174
8.4.3 MAC TX Statistics Register Overview .................................................................178
8.4.4 PHY Autoscan Registers.....................................................................................181
8.4.5 Global Status and Configuration Register Overview ...........................................188
8.4.6 RX FIFO Register Overview ................................................................................193
8.4.7 TX FIFO Register Overview.................................................................................203
8.4.8 MDIO Register Overview.....................................................................................211
8.4.9 SPI3 Register Overview.......................................................................................213
8.4.10 SerDes Register Overview ..................................................................................220
8.4.11 Optical Module Register Overview ......................................................................222