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IXF1104 4-Port Gigabit Ethernet Media Access Controller
219 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Table 148. Address Parity Error Packet Drop Counter ($0x70A)
Bit Name Description Type
1
Default
Register Description:
This register counts the number of packets dropped due to parity error
detection during the address selection cycle.
0x00000000
31:8 Reserved Reserved RO 0x000000
7:0
Address Parity Error
Packet Drop Counter
This is an 8-bit counter that counts the number of
packets dropped due to parity error detection
during the address selection cycle. This gets
cleared when read and saturates at 8’hFF. There
is only one counter for address parity drop as
address will be used only in MPHY mode of
operation. The counter gets cleared once the
register is read.
R0x00
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write