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IXF1104 4-Port Gigabit Ethernet Media Access Controller
Datasheet 196
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Table 122. RX FIFO Port Reset ($0x59E)
Bit Name Description Type
1
Default
Register Description:
The soft reset register for each port in the RX block. Port ID = bit
position in the register. To make the reset active, the bit must be set High. For example, reset
of port 1 implies register value = 0000_0018. Setting the bit to 0 de-asserts the reset.
0x00000000
31:4 Reserved Reserved RO 0x0000000
3
Reset RX FIFO for
Port 3
Port 3
0 = De-assert reset
1 = Reset
R/W 0
2
Reset RX FIFO for
Port 2
Port 2
0 = De-assert reset
1 = Reset
R/W 0
1
Reset RX FIFO for
Port 1
Port 1
0 = De-assert reset
1 = Reset
R/W 0
0
Reset RX FIFO for
Port 0
Port 0
0 = De-assert reset
1 = Reset
R/W 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 123. RX FIFO Errored Frame Drop Enable ($0x59F) (Sheet 1 of 2)
Bit Name Description Type
1
Default
Register Description:
This register configures the dropping of error packets (DEBAD).
NOTE: Jumbo packets are not dropped.
0x00000000
31:4 Reserved Reserved RO 0x0000000
3
RX FIFO Errored
Frame Drop Enable
Port 3
This bit is used in conjunction with MAC filter bits.
This allows the user to select whether the errored
packets are to be dropped or not.
1 = Frame Drop Enable
0 = Frame Drop Disable
R/W 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write