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IXF1104 4-Port Gigabit Ethernet Media Access Controller
Datasheet 192
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Table 112. JTAG ID ($0x50C)
Bit Name Description Type
1
Default
Register Description:
The value of this register follows the same scheme as the device
identification register found in the IEEE 1149.1 specification. The upper four bits correspond to
silicon stepping. The next 16 bits store a Part ID Number. The next 11 bits contain a JEDEC
manufacturer ID. Bit zero = 1 if the chip is the first in a stack. The encoding scheme used for
the Product ID field is implementation-dependent.
0x10450013
31:28 Version Version RO 0001
2
27:12 Part ID Part ID RO
0000010001
010000
11:8
JEDEC Continuation
Characters
JEDEC Continuation Characters RO 0000
7:1 JEDEC ID JEDEC ID RO 0001001
0Fixed Fixed RO 1
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
2. These bits vary with stepping.