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CHAPTER 15 INSTRUCTION SET
User’s Manual U12978EJ3V0UD
203
Mnemonic Operands Bytes Clocks Operation Flag
ZACCY
MOVW rp,#word 3 6 rp ← word
AX,saddrp 2 6 AX ← (saddrp)
saddrp,AX 2 8 (saddrp) ← AX
AX,rp
Note
1 4 AX ← rp
rp,AX
Note
14rp ← AX
XCHW AX,rp
Note
1 8 AX ↔ rp
ADD A,#byte 2 4 A,CY ← A+byte ×××
saddr,#byte 3 6 (saddr),CY ← (saddr) + byte ×××
A,r 2 4 A,CY ← A+r ×××
A,saddr 2 4 A,CY ← A+(saddr) ×××
A,!addr16 3 8 A,CY ← A+(addr16) ×××
A,[HL] 1 6 A,CY ← A+(HL) ×××
A,[HL+byte] 2 6 A,CY ← A+(HL+byte) ×××
ADDC A,#byte 2 4 A,CY ← A+byte+CY ×××
saddr,#byte 3 6 (saddr),CY ← (saddr)+byte+CY ×××
A,r 2 4 A,CY ← A+r+CY ×××
A,saddr 2 4 A,CY ← A+(saddr)+CY ×××
A,!addr16 3 8 A,CY ← A+(addr16)+CY ×××
A,[HL] 1 6 A,CY ← A+(HL)+CY ×××
A,[HL+byte] 2 6 A,CY ← A+(HL+byte)+CY ×××
SUB A,#byte 2 4 A,CY ← A−byte ×××
saddr,#byte 3 6 (saddr), CY ← (saddr)− byte ×××
A,r 2 4 A,CY ← A−r ×××
A,saddr 2 4 A,CY ← A− (saddr) ×××
A,!addr16 3 8 A,CY ← A−(addr16) ×××
A,[HL] 1 6 A,CY ← A−(HL) ×××
A,[HL+byte] 2 6 A,CY ← A−(HL+byte) ×××
Note Only when rp = BC, DE, or HL.
Remark One instruction clock cycle is one CPU clock cycle (fCPU
) selected by the processor clock control
register (PCC).