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Cavium Processor Complex: PCI
ATCA-9305 User’s Manual 10009109-01
3-4
Cavium Reset
Each CN5860 can be reset independently of the other processor without affecting its opera-
tion. This task is performed by the MPC8548 management processor.
Figure 3-2: CN5860 Reset Diagram
Voltage
Monitor
Delay
IPMC
Stratix II GX
XAUI #2
P1 DDR
SDRAM
Stratix II GX
XAUI #1
Stratix II GX
XAUI #4
Stratix II GX
XAUI #3
KSL
CPLD
P1_RESET*
CN5860
Cavium
Processor 1
P1_PCI_RST*
P1_PWRGD
P1_DDR_RST*
MIP1_RST*
MIP2_RST*
MIP3_RST*
MIP4_RST*
CN5860
Cavium
Processor 2
P2_RESET*
P2_PCI_RST*
P2_PWRGD
P2 DDR
SDRAM
P2_DDR_RST*
IPMP
CPLD
PWRGD_OK
L_PAYLD_EN
3_3V_PWRGD
2_5V_PWRGD
1_8V_PWRGD
1_2V_PWRGD
1_0V_PWRGD
PQ_CORE_PWRGD
P1_CORE_PWRGD
P2_CORE_PWRGD
POR_RST*
48A_OK
48B_OK
E_HANDLE
I2C IO
Port
L_PAYLOAD_RST*
PRIV_I2C_SCL
PRIV_I2C_SDA
IPMC_PO_RST*
3_3V_MP
MC Reset
3_3V_MP
Hot Swap
Switch
3_3V_MP
3_3V_MP
Front
Panel
Reset
3_3V
Voltage
Monitor
Delay
33MHz
IPMC_PO_RST*