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Register Description
D15343-003 105
4.11.9 HDR – Header Type Register (Device #2)
This register contains the Header Type of the IGD.
4.11.10 GMADR – Graphics Memory Range Address Register (Device #2)
IGD graphics system memory base address is specified in this register.
Bit Description
7:0 Master Latency Timer Count Value – RO
Address Offset:
Default Value:
Access:
Size:
0Eh
00h
Read Only
8 bits
Bit Description
7 Multi Function Status (MFunc): Indicates if the device is a multi-function device.
6:0 Header Code (H): This is a 7-bit value that indicates the Header code for the IGD. This code has
the value 00h, indicating a type 0 configuration space format.
Address Offset:
Default Value:
Access:
Size:
10-13h
00000008h
Read/Write, Read Only
32 bits
Bit Description
31:27 Memory Base Address–R/W: Set by the OS, these bits correspond to address signals [31:26].
26 128-MB Address Mask – RO: 0 indicates 128-MB address
25:4 Address Mask–RO: Indicates (at least) a 32-MB address range.
3 Prefetchable Memory–RO: Enable prefetching.
2:1 Memory Type–RO: Indicates 32-bit address.
0 Memory/IO Space–RO: Indicates System Memory Space.