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82854 Graphics Memory Controller Hub (GMCH)
120 D15343-003
5.4.5.1 PCI I/O Address Mapping
The GMCH can be programmed to direct non-memory (I/O) accesses to the PCI bus interface
when CPU initiated I/O cycle addresses are within the I/O address range. This range is controlled
via the I/O Base Address (IOBASE) and I/O Limit Address (IOLIMIT) registers in GMCH
Device #1 configuration space.
Address decoding for this range is based on the following concept. The top 4 bits of the respective
I/O Base and I/O Limit registers correspond to address bits A[15:12] of an I/O address. For the
purpose of address decoding, the GMCH assumes that lower 12 address bits A[11:0] of the I/O
base are zero and that address bits A[11:0] of the I/O limit address are FFFh. This forces the I/O
address range alignment to 4-kB boundary and produces a size granularity of 4 kB.
The GMCH positively decodes I/O accesses to AGP I/O address space as defined by the following
equation:
I/O_Base_Address ≤ CPU I/O Cycle Address ≤ I/O_Limit_Address
The effective size of the range is programmed by the plug-and-play configuration software and it
depends on the size of I/O space claimed by the AGP device.
In Native Graphics mode, the GMCH also forwards accesses to the Legacy VGA I/O ranges
according to the settings in the Device #1 configuration registers BCTRL (VGA Enable) and
PCICMD1 (IOAE1), unless a second adapter (monochrome) is present on the Hub interface/PCI
(or ISA). The presence of a second graphics adapter is determined by the MDAP configuration bit.
When MDAP is set, the GMCH will decode legacy monochrome IO ranges and forward them to
the Hub interface. The IO ranges decoded for the monochrome adapter are 3B4h, 3B5h, 3B8h,
3B9h, 3Bah and 3BFh.
Note: The GMCH Device #1 I/O address range registers defined above are used for all I/O space
allocation for any devices requiring such a window on PCI. These devices would include the AGP
device, PCI-66MHz/3.3V agents, and multifunctional AGP devices where one or more functions
are implemented as PCI devices.
The PCICMD1 register can disable the routing of I/O cycles to PCI.
5.4.6 GMCH Decode Rules and Cross-Bridge Address Mapping
The address map described above applies globally to accesses arriving on any of the three
interfaces (e.g., Host bus, IGD, and Hub interface).