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Register Description
D15343-003 53
4.8.4 PCI Status Register
PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0's PCI
Interface. Bit 14 is Read/Write Clear. All other bits are Read Only. Since GMCH Device #0 does
not physically reside on PCI_A many of the bits are not implemented.
Address Offset:
Default Value:
Access:
Size:
06-07h
0090h
Read only, Read/WriteClear
16 bits
Bit Descriptions
15 Detected Parity Error (DPE): The GMCH does not implement this bit and it is hardwired to a 0.
Writes to this bit position have no effect.
14 Signaled System Error (SSE): R/WC. This bit is set to 1 when GMCH Device #0 generates an
SERR message over HI for any enabled Device #0 error condition. Device #0 error conditions are
enabled in the PCICMD and ERRCMD registers. Device #0 error flags are read/reset from the
PCISTS or ERRSTS registers. Software sets SSE to 0 by writing a 1 to this bit.
13 Received Master Abort Status (RMAS): R/WC. This bit is set when the GMCH generates a HI
request that receives a Master Abort completion packet or Master Abort Special Cycle. Software
clears this bit by writing a 1 to it.
12 Received Target Abort Status (RTAS): R/WC. This bit is set when the GMCH generates a HI
request that receives a Target Abort completion packet or Target Abort Special Cycle. Software
clears this bit by writing a 1 to it. If bit 6 in the ERRCMD is set to a one and an Serr# special cycle
is generated on the HI bus.
11 Signaled Target Abort Status (STAS): The GMCH will not generate a Target Abort HI
completion packet or Special Cycle. This bit is not implemented in the GMCH and is hardwired to
a 0. Writes to this bit position have no effect.
10:9 DEVSEL Timing (DEVT): These bits are hardwired to “00”. Writes to these bit positions have no
affect. Device #0 does not physically connect to PCI_A. These bits are set to “00” (fast decode)
so that the GMCH does not limit optimum DEVSEL timing for PCI_A.
8 Master Data Parity Error Detected (DPD): PERR signaling and messaging are not implemented
by the GMCH therefore this bit is hardwired to 0. Writes to this bit position have no effect.
7 Fast Back-to-Back (FB2B): This bit is hardwired to 1. Writes to these bit positions have no
effect. Device #0 does not physically connect to PCI_A. This bit is set to 1 (indicating fast back-to-
back capability) so that the GMCH does not limit the optimum setting for PCI_A.
6:5 Reserved
4 Capability List (CLIST): This bit is hardwired to 1 to indicate to the configuration software that
this device/function implements a list of new capabilities. A list of new capabilities is accessed via
register CAPPTR at configuration address offset 34h.
3:0 Reserved