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Intel
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82854 Graphics Memory Controller Hub (GMCH)
124 D15343-003
MSI is dependent on the address of the interrupt Memory Write. The GMCH forwards inbound
Hub interface memory writes to address 0FEEx_xxxxh, to the system bus as Interrupt Message
transactions.
6.2.2 Upstream Interrupt Messages
The GMCH accepts message based interrupts from its Hub interface and forwards them to the
system bus as Interrupt Message transactions. The Interrupt Messages presented to the GMCH are
in the form of Memory Writes to address 0FEEx_xxxxh. At the Hub interface, the Memory Write
Interrupt Message is treated like any other Memory Write; it is either posted into the inbound data
buffer (if space is available) or retried (if data buffer space is not immediately available). Once
posted, the Memory Write from the Hub interface, to address 0FEEx_xxxxh, is decoded as a cycle
that needs to be propagated by the GMCH to the front side bus as an Interrupt Message transaction.
6.3 System Memory Interface
6.3.1 DDR SDRAM Interface Overview
The GMCH supports DDR SDRAM at 200/266-MHz and includes the following support:
• Up to 1 GB of PC2100/PC2700 DDR SDRAM
• Maximum of two DDR DIMMs, single-sided and/or double-sided
The 2-bank select lines SBA[1:0] and the 13 Address lines SMA[12:0] allow the GMCH to support
64-bit wide DDR DIMMs using 128-Mb, 256-Mb, and 512-Mb DDR SDRAM technology. While
address lines SMA[9:0] determine the starting address for a burst, burst length can only be 4. Four
chip selects SCS[3:0]# lines allow a maximum of two rows of single-sided DDR SDRAM DIMMs
and four rows of double-sided DDR SDRAM DIMMs.
The GMCH main system memory controller targets CAS latencies of 2 and 2.5 for DDR SDRAM.
The GMCH provides refresh functionality with a programmable rate (normal DDR SDRAM rate is
1 refresh/15.6 µs). For write operations of less than a full cache line, GMCH will perform a cache-
line read and into the write buffer and perform byte-wise write-merging in the write buffer.
6.3.2 System Memory Organization and Configuration
6.3.2.1 Configuration Mechanism for DDR DIMMs
Detection of the type of DDR SDRAM installed on the DDR DIMM is supported via Serial
Presence Detect mechanism as defined in the JEDEC 200-pin DDR DIMM specification.
Before any cycles to the system memory interface can be supported, the GMCH DDR SDRAM
registers must be initialized. The GMCH must be configured for operation with the installed
system memory types. Detection of system memory type and size is done via the System
Management Bus (SMB) interface on the ICH4-M. This two-wire bus is used to extract the DDR
SDRAM type and size information from the Serial Presence Detect port on the DDR SDRAM
DDR DIMMs. DDR SDRAM DIMMs contain a 5-pin Serial Presence Detect interface, including
SCL (serial clock), SDA (serial data) and SA[2:0]. Devices on the SMBus have a 7-bit address.
For the DDR SDRAM DIMMs, the upper four bits are fixed at 1010b. The lower three bits are
strapped on the SA[2:0] pins. SCL and SDA are connected directly to the System Management bus
on the ICH4-M. Thus data is read from the Serial Presence Detect port on the DDR DIMMs via a