Intel D15343-003 Switch User Manual


 
Intel
®
82854 Graphics Memory Controller Hub (GMCH)
116 D15343-003
5.4.2.1 Extended SMRAM Address Range (HSEG and TSEG)
The HSEG and TSEG SMM transaction address spaces reside in this extended system memory
area.
5.4.2.2 HSEG
SMM mode CPU accesses to enabled HSEG are remapped to 000A0000h-000BFFFFh. Non-SMM
mode CPU accesses to enabled HSEG are considered invalid are terminated immediately on the
FSB. The exceptions to this rule are Non-SMM mode Write Back cycles that are remapped to
SMM space to maintain cache coherency. Hub interface originated cycles to enabled SMM space
are not allowed. Physical DDR SDRAM behind the HSEG transaction address is not remapped and
is not accessible.
5.4.2.3 TSEG
TSEG is 1-MB in size and is at the top of physical system memory. SMM mode CPU accesses to
enabled TSEG access the physical DDR SDRAM at the same address. Non-SMM mode CPU
accesses to enabled TSEG are considered invalid and are terminated immediately on the FSB. The
exceptions to this rule are Non-SMM-mode Write Back cycles that are directed to the physical
SMM space to maintain cache coherency. Hub interface originated cycles that enable SMM space
are not allowed.
The size of the SMRAM space is determined by the USMM value in the SMRAM register. When
the extended SMRAM space is enabled, non-SMM CPU accesses and all other accesses in this
range are forwarded to the Hub interface. When SMM is enabled the amount of system memory
available to the system is equal to the amount of physical DDR SDRAM minus the value in the
TSEG register.
5.4.2.4 Dynamic Video Memory Technology (DVMT)
The IGD supports DVMT in a non-graphics system memory configuration. DVMT is a mechanism
that manages system memory and the internal graphics device for optimal graphics performance.
DVMT-enabled software drivers, working with the memory arbiter and the operating system,
utilize the system memory to support 2D graphics and 3D applications. DVMT dynamically
responds to application requirements by allocating the proper amount of display and texturing
memory.