Filter
Top Products
Intel
®
82854 Graphics Memory Controller Hub (GMCH)
142 D15343-003
6.5.3.2 ARIB 960 X 540 support
In order to support the conversion of a 960x540 or a 960x1080 Plane A buffer to 1920x1080i, the
GMCH supports pixel doubling in the horizontal direction and field replication in the vertical
direction. In order to activate this functionality, interlace mode bit 20 in the DVOC- Digital
Display Port C Register must be programmed to a 1. Register DSPACNTR-Display A Plane
Control Register bits 21:20 are used to program the pixel doubling functionality. The following
depicts the bit programming:
00 - No pixel/line multiplication
01 - Pixel AND Line doubling (not valid in interlaced mode)
10 - Reserved
11 - Pixel doubling ONLY (not validated in Native Graphic Mode)
The Field replication mode is used to create two fields of data from Plane A. This is accomplished
by scanning out Plane A once to produce Field1 and then rescanned out to produce Field2. In
normal interlaced mode, the DSPABASE Register is programmed to the frame buffer start address,
the DSPASTER Register is programmed with the frame buffer start address plus one line, and the
DSPASTRIDE Register is programmed to 2x the line increment of the image in the frame buffer.
For Field1, the DSPABASE and DSPASTRIDE Registers generate addresses into the frame buffer
for even lines of the image. For Field2, the DSPASTER and DSPASTRIDE Registers generate
addresses into the frame buffer to read odd lines of the image. In field replication mode, the
DSPABASE and DSPASTER Registers are programmed with the same start address of the image
in the frame buffer. The DSPASTRIDE register is programmed to the 1x line-to-line increment
value. With interlaced mode enabled, this will effectively scan out the identical frame buffer for
both Field1 and Field2.
Please note that programming bits 21:20 of the DSPACNTR Register to "01" while the interlaced
mode is enabled is illegal. In other words, Line doubling is undefined for the interlaced mode of
operation.
In order to archieve this, program the PLL to generate Dpclk/2 internally when the following bits
of the DSPACNTR-Display A Plane Control Register, bit 21:20, are programmed for pixel
duplication mode.