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Intel
®
82854 Graphics Memory Controller Hub (GMCH)
108 D15343-003
4.11.16 INTRLINE – Interrupt Line Register (Device #2)
4.11.17 INTRPIN – Interrupt Pin Register (Device #2)
4.11.18 MINGNT – Minimum Grant Register (Device #2)
Address Offset:
Default Value:
Access:
Size:
3Ch
00h
Read/Write
8 bits
Bit Description
7:0 Interrupt Connection: Used to communicate interrupt line routing information. POST software
Writes the routing information into this register as it initializes and configures the system. The value
in this register indicates which input of the System Interrupt controller that the device’s interrupt pin
is connected to.
Address Offset:
Default Value:
Access:
Size:
3Dh
01h
Read Only
8 bits
Bit Description
7:0 Interrupt Pin: As a single function device, the IGD specifies INTA# as its interrupt pin. 01h=INTA#.
For Function #1, this register is set to 00h.
Address Offset:
Default Value:
Access:
Size:
3Eh
00h
Read Only
8 bits
Bit Description
7:0 Minimum Grant Value: The IGD does not burst as a PCI compliant master.