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82854 GMCH System Address Map
D15343-003 121
5.4.7 Hub Interface Decode Rules
The GMCH accepts accesses from Hub interface to the following address ranges:
• All Memory Read and Write accesses to Main DDR SDRAM including PAM region (except
SMM space)
• Memory writes to VGA range (Native Graphics Mode only)
All Memory Reads from the Hub interface A that are targeted > 4-GB system memory range will
be terminated with Master Abort completion, and all Memory Writes (>4-GB) from the Hub
interface will be ignored.
Hub interface system memory accesses that fall elsewhere within the system memory range are
considered invalid and will be remapped to system memory address 0h, snooped on the Host Bus,
and dispatched to DDR SDRAM. Reads will return all 1's with Master Abort completion. Writes
will have BE's deasserted and will terminate with Master Abort if completion is required. I/O
cycles will not be accepted. They are terminated with Master Abort completion packets.
5.4.7.1 Hub Interface Accesses to GMCH that Cross Device Boundaries
Hub interface accesses are limited to 256 B (Bytes) but have no restrictions on crossing address
boundaries. A single Hub interface request may therefore span device boundaries (DDR SDRAM)
or cross from valid addresses to invalid addresses (or visa versa). The GMCH does not support
transactions that cross device boundaries. For Reads and for Writes requiring completion, the
GMCH will provide separate completion status for each naturally aligned 32-B or 64-B block. If
the starting address of a transaction hits a valid address, the portion of a request that hits that target
device (DDR SDRAM) will complete normally. The remaining portion of the access that crosses a
device boundary (targets a different device than that of the starting address) or hits an invalid
address will be remapped to system memory address 0h, snooped on the Host Bus, and dispatched
to DDR SDRAM. Reads will return all 1's with Master Abort completion. Writes will have BE's
(Byte Enable) deasserted and will terminate with Master Abort if completion is required.
If the starting address of a transaction hits an invalid address the entire transaction will be
remapped to system memory address 0h, snooped on the Host Bus, and dispatched to DDR
SDRAM. Reads will return all 1's with Master Abort completion. Writes will have BE's deasserted
and will terminate with Master Abort if completion is required.