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Intel
®
82854 Graphics Memory Controller Hub (GMCH)
88 D15343-003
4.9.17 DTC – DRAM Throttling Control Register (Device #0)
Throttling is independent for system memory banks, GMCH Writes, and Thermal Sensor Trips.
Read and Write Bandwidth is measured independently for each bank. If the number of Octal -
Words (16 bytes) Read/Written during the window defined below (Global DDR SDRAM Sampling
Window: GDSW) exceeds the DDR SDRAM Bandwidth Threshold, then the DDR SDRAM
Throttling mechanism will be invoked to limit DDR SDRAM Reads/Writes to a lower bandwidth
checked over smaller time windows. The throttling will be active for the remainder of the current
GDSW and for the next GDSW after which it will return to Non-Throttling mode. The throttling
mechanism accounts for the actual bandwidth consumed during the sampling window, by reducing
the allowed bandwidth within the smaller throttling window based on the bandwidth consumed
during the sampling period. Although bandwidth from/to independent rows and GMCH Write
bandwidth is measured independently, once Tripped all transactions except high priority graphics
Reads are subject to throttling.
Address Offset:
Default Value:
Access:
Size:
A0-A3h
00000000h
Read/Write/Lock
32 bits