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82854 Graphics Memory Controller Hub (GMCH)
118 D15343-003
5.4.3 System Management Mode (SMM) Memory Range
The GMCH supports the use of main system memory as System Management RAM (SMM RAM)
enabling the use of System Management mode. The GMCH supports three SMM options:
Compatible SMRAM (C_SMRAM), High Segment (HSEG), and Top of Memory Segment
(TSEG). System Management RAM space provides a system memory area that is available for the
SMI handler's and code and data storage. This system memory resource is normally hidden from
the system OS so that the processor has immediate access to this system memory space upon entry
to SMM. The GMCH provides three SMRAM options:
• Below 1-MB option that supports compatible SMI handlers.
• Above 1-MB option that allows new SMI handlers to execute with Write-back cacheable
SMRAM.
• Above 1-MByte solutions require changes to compatible SMRAM handlers code to properly
execute above 1 MByte.
Note: Hub interface is not allowed to access the SMM space.
5.4.3.1 SMM Space Restrictions
If any of the following conditions are violated the results of SMM accesses are unpredictable and
may cause the system to hang:
• The Compatible SMM space must not be set-up as cacheable.
• High or TSEG SMM transaction address space must not overlap address space assigned to
DDR SDRAM or to any PCI devices (including Hub interface and graphics devices). This is a
BIOS responsibility.
• Both D_OPEN and D_CLOSE must not be set to 1 at the same time.
• When TSEG SMM space is enabled, the TSEG space must not be reported to the OS as
available. This is a BIOS responsibility.
5.4.3.2 SMM Space Definition
SMM space is defined by its addressed SMM space and its DDR SDRAM SMM space. The
addressed SMM space is defined as the range of bus addresses used by the CPU to access SMM
space. DDR SDRAM SMM space is defined as the range of physical DDR SDRAM locations
containing the SMM code. SMM space can be accessed at one of three transaction address ranges:
Compatible, High, and TSEG. The Compatible and TSEG SMM space is not remapped and
therefore the addressed and DDR SDRAM SMM space is the same address range. Since the High
SMM space is remapped the addressed and DDR SDRAM SMM space is a different address range.
Note that the High DDR SDRAM space is the same as the Compatible Transaction Address space.
Table 28 describes three unique address ranges:
• Compatible Transaction Address (Adr C)
• High Transaction Address (Adr H)
• TSEG Transaction Address (Adr T)
These abbreviations are used later in Table 28.