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Intel
®
82854 Graphics Memory Controller Hub (GMCH)
138 D15343-003
6.5 Internal Graphic Display Interface
The GMCH has three dedicated display ports: an Analog CRT port and two Digital display ports,
DVOB and DVOC.
When the GMCH is strapped to operate in Native Graphic Mode, the DVOB and DVOC can
support down stream devices such as TV-out encoders, external DACs, LVDS transmitters, and
TMDS transmitters. Each display port has control signals that may be used to control, configure
and/or determine the capabilities of an external device. The data that is sent out the display ports
are selected from one of the two possible sources, display pipe A or display pipe B.
The GMCH's digital display port is capable of driving a 165-MHz pixel clock on a single DVO
port, or a 330-MHz pixel clock by combining DVOB and DVOC.
6.5.1 Pipe A Timing Generator Unit
The Pipe A Timing generator provides the basic timing information for Display Pipe A. Timings
are composed of blank, sync, border and active periods. The active period represents the data area;
this is normally the size of a fixed resolution display or the selected resolution. Sync happens only
within blank periods thereby dividing the blank into three regions consisting of a front porch, sync
time, and back porch. Borders only happen directly before the start of blank and directly after the
end of blank. Borders are referred to as left, right, top, or bottom. The Pipe A timing generator has
been adapted to offer interlace support for the generation of HSYNC and VSYNC relative timing
to support downstream field identification. It has also been adapted to provide interlace timing
support for 480i and PAL formats. The following sections detail the features supported by the
Intel
®
82854 GMCH.