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R61509V Target Spec
Rev. 0.11 April 25, 2008, page 117 of 181
When transferring data in synchronization with FMARK signal, minimum RAM data write speed and
internal clock frequency must be taken into consideration. They must be more than the values calculated
from the following equations.
iancevar)clocks(23))BP(BackPorch)FP(FrontPorch)NL(esDisplayLin(encyFrameFrequ
) [Hz] ency (fosclock frequInternal c
××++×=
fosc
1
)clocks(16)insargm)NL(esDisplayLin)BP(BackPorch)FP(FrontPorch(
)NL(esDisplayLin240
]Hz.)[(mineedRAMWriteSp
××−++
×
>
Note: When RAM write operation is not started immediately following the rising edge of FMARK, the
time from the rising edge of FMARK until the start of RAM write operation must also be taken into
account.
Examples of calculating minimum RAM data write speed and internal clock frequency is as follows.
[Example]
Panel size 240 RGB
×
432 lines (NL = 6’h35: 432 lines)
Total number of lines (NL) 432 lines
Back/front porch 14/2 lines (BP = 4h’E, FP = 4’h2)
Frame marker position (FMP) Display end line: 432
nd
line (FMP = 9’h1BF)
Frame frequency 60 Hz
Internal oscillation frequency 678kHz
Internal oscillation frequency (fosc) [Hz] = 678kHz × 1.07 / 1.0 = 726 kHz
(variance is taken into account)
Notes: 1.When setting the internal clock frequency, possible causes of fluctuation must also be taken into
consideration. In this example, the internal clock frequency allows for a margin of ±7% for
variances and guarantee that display operation is completed within one FMARK cycle.
2.This example includes variances attributed to LSI fabrication process and room temperature.
Other possible causes of variances, such as differences in external resistors and voltage change
are not considered in this example. It is necessary to include a margin for these factors.
Minimum speed for RAM writing [Hz]
>
240
×
320 / {((2+14
+
320 – 2) lines
×
16 clocks)
×
1/726 kHz} = 7.4 MHz
Notes: 1. In this example, it is assumed that the R61509V starts writing data in the internal RAM on the
rising edge of FMARK.
2.There must be at least a margin of 2 lines between the line to which the R61509V has just written
data and the line where display operation on the LCD is performed.
3.The FMARK signal output position is set to the line specified by FMP[8:0] bits.
In this example, RAM write operation at a speed of 7.4MHz or more, when starting on the rising edge of
FMARK, guarantees the completion of data write operation in a certain line address before the R61509V