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R61509V Target Spec
Rev. 0.11 April 25, 2008, page 124 of 181
RGB Interface Timing
The timing relationship of signals in RGB interface operation is as follows.
16-/18-Bit RGB Interface Timing
1H
1 clock
1H or more
One frame
Back porch period Front porch period
HLW ҈ 1CLK
DTST
҈ 1CLK
VSYNCX
HSYNCX
DOTCLK
ENABLE
DB17-0
VSYNCX
HSYNCX
DOTCLK
ENABLE
DB17-0
Valid data
Figure 45
Note: VLW: VSYNCX Low period
HLW: HSYNCX Low period
DTST: data transfer setup time