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1.1Introduction
1.2BlockDiagram
JTAG Interface
System Control
PLLs/Clock Generator
Input
Clock(s)
Power/Sleep Controller
Pin Multiplexing
DSP Subsystem
C64x+t DSP CPU
32 KB
L1 Pgm
128 KB L2 RAM
80 KB
L1 Data
BT.656,
Y/C,
Raw (Bayer)
Video Processing Subsystem (VPSS)
CCD
Controller
Video
Interface
Front End
Resizer
Histogram/
3A
Preview
10b DAC
On-Screen
Display
(OSD)
Video
Encoder
(VENC)
10b DAC
10b DAC
10b DAC
Back End 8b BT.656,
Y/C,
24b RGB
NTSC/
PAL,
S-Video,
RGB,
YPbPr
Switched Central Resource (SCR)
Peripherals
EDMA
I
2
C HECC UART
Serial Interfaces
DDR2
Mem Ctlr
(32b)
Async EMIF/
NAND/
(8b)
Program/Data Storage
Watchdog
Timer
PWM
System
General-
Purpose
Timer
PCI
(33 MHz)
VLYNQ
EMAC
With
MDIO
Connectivity
HPI
McASP McBSP
OSC
Boot ROM
16b
GPIO
Introduction
TheTMS320DM643xDigitalMediaProcessor(DMP)containsapowerfulDSPtoefficientlyhandleimage,
video,andaudioprocessingtasks.TheDM643xDMPconsistsofthefollowingprimarycomponentsand
sub-systems:
•DSPSubsystem(DSPSS),includingtheC64x+Megamoduleandassociatedmemory.
•VideoProcessingSubsystem(VPSS),includingtheVideoProcessingFrontEnd(VPFE)Subsystem,
ImageInputandImageProcessingSubsystem,andtheVideoProcessingBackEnd(VPBE)Display
Subsystem
•AsetofI/Operipherals
•ApowerfulDMAsubsystemandDDR2memorycontrollerinterface
TheDSPsubsystemincludesTI’sstandardTMS320C64x+Megamoduleandseveralblocksofinternal
memory(L1P,L1D,andL2).
Formoreinformation,seetheTMS320C64x+DSPMegamodulePeripheralsReferenceGuide
(SPRU871),theTMS320C64x/C64x+DSPCPUandInstructionSetReferenceGuide(SPRU732),andthe
TMS320C64x+DSPCacheUser’sGuide(SPRU862).
AnexampleblockdiagramfortheTMS320DM643xDMPisshowninFigure1-1.
Figure1-1.TMS320DM643xDMPBlockDiagram
Introduction12SPRU978E–March2008
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