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9.6.2EDMATransferControllerConfiguration
9.7BootControl
BootControl
Eachswitchedcentralresource(SCR)performsprioritizationbasedontheprioritylevelofthemasterthat
sendsthecommand.Eachbusmaster'spriorityisprogrammedinthechip-levelBusMasterPriority
ControlRegisters(MSTPRI0orMSTPRI1).Thedefaultprioritylevelforeachbusmasterisshownin
Table9-2.Applicationsoftwareisexpectedtomodifythesevaluestoobtainthedesiredsystem
performance.
Table9-2.TMS320DM643xDMPDefaultMasterPriorities
MasterDefaultPriority
VPSS0
(1)
EDMACh00
(2)
EDMACh10
(2)
EDMACh20
(2)
DSP(DMA)7
(3)
DSP(CFG)1
EMAC4
VLYNQ4
PCI4
(1)
DefaultvalueinVPSSPCRregister
(2)
DefaultvalueinEDMAQUEPRIregister
(3)
DefaultvalueinDSPMDMAARBE.PRIfield
TheEDMAtransfercontrollerdefaultburstsizeconfigurationregister(EDMATCCFG)intheSystem
moduleconfiguresthedefaultburstsizefortheEDMAtransfercontrollers(EDMATC0,EDMATC1,and
EDMATC2).Refertothedevice-specificdatamanualformoreinformationonthisregister.
TheSystemModulecontainsthefollowingbootcontrolregisters:
•DeviceBootConfigurationRegister(BOOTCFG)
•BootCompleteRegister(BOOTCMPLT)
•DSPBootAddressRegister(DSPBOOTADDR)
SeeChapter11andthedevice-specificdatamanualfordescriptionsoftheseregisters.
SPRU978E–March2008SystemModule89
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