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9.43.3VI/OPower-DownControl
9.5PeripheralStatusandControl
9.5.1TimerControl
9.5.2VPSSClockandDACControl
9.5.3DDR2VTPControl
9.5.4HPIControl
3.3VI/OPower-DownControl
TheVDD3P3V_PWDNregistercontrolspowertothe3.3VI/Ocells.Some3.3VI/Osdefaulttopower
downforpowersaving.Seedevice-specificdatamanualforthedescriptionoftheVDD3P3V_PWDN
register.
SeveraloftheDM643xDMPperipheralmodulesrequireadditionalsystem-levelcontrollogic.Those
registersarediscussedinthissection.
TheTimercontrolregister(TIMERCTL)providesadditionalcontrolforTimer0andTimer2(Watchdog
Timer).Seethedevice-specificdatamanualfordetailsonthisregister.
Clocksforthevideoprocessingsubsystem(VPSS)arecontrolledviatheVPSSclockcontrolregister
(VPSS_CLKCTL).Seethedevice-specificdatamanualfordetailsonthisregister.
TheDDR2VTPEnableRegister(DDRVTPER)isusedalongwithotherregistersintheVTPIObuffer
calibrationprocessfortheDDR2memorycontroller.Seethedevice-specificdatamanualforthelocation
ofthisregister.SeetheTMS320DM643xDMPDDR2MemoryControllerUser'sGuide(SPRU986)for
moredetailsontheVTPIObuffercalibrationprocess.
TheHPIControlRegister(HPICTL)controlsthehostburstwritetime-outvalueforHPIoperation.Seethe
device-specificdatamanualfordetailsonthisregister.
SPRU978E–March2008SystemModule87
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