Filter
Top Products
www.ti.com
5.3.2.3ChangingPLLMultiplier
PLL2Control
IfthePLLisnotpowereddown(PLLPWRDNbitinPLLCTLisclearedto0)andthePLLstabilizationtime
ispreviouslymet(step7inSection5.3.2.2),followthisproceduretochangePLL2multiplier.
1.BeforechangingthePLLfrequency,switchtoPLLbypassmode:
a.ClearthePLLENSRCbitinPLLCTLto0toallowPLLCTL.PLLENtotakeeffect.
b.ClearthePLLENbitinPLLCTLto0(selectPLLbypassmode).
c.Waitfor4MXIcyclestoensurePLLCswitchestobypassmodeproperly.
2.ClearthePLLRSTbitinPLLCTLto0(resetPLL).
3.ClearthePLLDISbitinPLLCTLto0(enablethePLL)toallowPLLoutputstostarttoggling.Notethat
thePLLCisstillatPLLbypassmode;therefore,thetogglingPLLoutputdoesnotgetpropagatedto
therestofthedevice.
4.ProgramtherequiredmultipliervalueinPLLM.
5.Ifnecessary,programPLLDIV1andPLLDIV2registerstochangetheSYSCLK1andSYSCLK2divide
values:
a.CheckfortheGOSTATbitinPLLSTATtoclearto0toindicatethatnoGOoperationiscurrentlyin
progress.
b.ProgramtheRATIOfieldinPLLDIV1andPLLDIV2withthedesireddividefactors.ForPLLC2,
thereisnospecificfrequencyratiorequirementsbetweenSYSCLK1andSYSCLK2.Makesurein
thisstepyouleavethePLLDIV1.D1ENandPLLDIV2.D2ENbitsset(default).
c.SettheGOSETbitinPLLCMDto1toinitiateanewdividertransition.Duringthistransition,
SYSCLK1andSYSCLK2arepausedmomentarily.
d.WaitforNnumberofPLLDIVnsourceclockcyclestoensuredividerchangeshavecompleted.See
Section5.3.2.4fortheformulaoncalculatingthenumberofcyclesN.
e.WaitfortheGOSTATbitinPLLSTATtoclearto0.
6.WaitforPLLtoresetproperly.Seethedevice-specificdatamanualforPLLresettime.
7.SetthePLLRSTbitinPLLCTLto1tobringthePLLoutofreset.
8.WaitforPLLtolock.Seethedevice-specificdatamanualforPLLlocktime.
9.SetthePLLENbitinPLLCTLto1toremovethePLLfrombypassmode.
PLLController 46SPRU978E–March2008
SubmitDocumentationFeedback