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6.3PowerDomainandModuleStates
6.3.1PowerDomainStates
6.3.2ModuleStates
PowerDomainandModuleStates
Note:TheeffectsofDSPlocalresetandDSPmoduleresethavenotbeenfullyvalidated;
therefore,theseresetsarenotsupportedandshouldnotbeused.Instead,thePORor
RESETpinsshouldbeusedtoresettheentireDSP.
Table6-1showsthestateofeachmoduleafterchipPower-onReset(POR),WarmReset(RESET),or
MaxReset.Thesestatesaredefinedinthefollowingsections.
Apowerdomaincanonlybeinoneoftwostates:ONorOFF,definedasfollows:
•ON:powertothepowerdomainison.
•OFF:powertothepowerdomainisoff.
IntheDM643xDMP,theAlwaysOnPowerDomainisalwaysintheONstatewhenthechipis
powered-on.
Amodulecanbeinoneoffourstates:Disable,Enable,SyncReset,orSwRstDisable.Thesefourstates
correspondtocombinationsofmoduleresetassertedorde-assertedandmoduleclockonoroff,as
showninTable6-2.
Table6-2.ModuleStates
ModuleStateModuleResetModuleClockModuleStateDefinition
EnableDe-assertedOnAmoduleintheenablestatehasitsmoduleresetde-assertedand
ithasitsclockon.Thisisthenormalrun-timestateforagiven
module.
DisableDe-assertedOffAmoduleinthedisablestatehasitsmoduleresetde-assertedand
ithasitsclockoff.Thisstateistypicallyusedfordisablingamodule
clocktosavepower.TheDM643xDMPisdesignedinfullstatic
CMOS,sowhenyoustopamoduleclock,itretainsthemodule's
state.Whentheclockisrestarted,themoduleresumesoperating
fromthestoppingpoint.
SyncResetAssertedOnAmoduleintheSyncResetstatehasitsmoduleresetassertedand
ithasitsclockon.Generally,softwareisnotexpectedtoinitiatethis
state.
SwRstDisableAssertedOffAmoduleintheSwResetDisablestatehasitsmodulereset
assertedandithasitsclocksettooff.Afterinitialpower-on,most
modulesareintheSyncRststatebydefault(seeTable6-1).
Generally,softwareisnotexpectedtoinitiatethisstate.
Note:ModuleResetisdefinedtocompletelyresetagivenmodule,sothatallhardwarereturnsto
itsdefaultstate.SeeChapter10formoreinformationonmodulereset.
Formoreinformationonpowermanagement,seeChapter7.
PowerandSleepController 64SPRU978E–March2008
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