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4.1Overview
4.2ClockDomains
4.2.1CoreDomains
Overview
TheDM643xDMPrequiresoneprimaryreferenceclock.Theprimaryreferenceclockcanbeeithercrystal
inputordrivenbyexternaloscillators.A27MHZcrystalattheMXI/CLKINpinisrecommendedforthe
systemPLLs,whichgeneratetheclocksfortheDSP,peripherals,DMA,andimagingperipherals.The
recommended27MHZinputenablesyoutousethevideoDACstodriveNTSC/PALtelevisionsignalsat
theproperfrequencies.
Fordetailedspecificationsonclockfrequencyandvoltagerequirements,seethedevice-specificdata
manual.
Therearetwoclockingmodes:
•PLLBypassMode-powersaving(devicedefaultstothismode)
•PLLMode-PLLmultipliesinputclockuptothedesiredoperatingfrequency
Theclockofthemajorchipsubsystemsmustbeprogrammedtooperateatfixedratiosoftheprimary
system/DSPclockfrequencywithineachmode,asshowninTable4-1.TheDM643xDMPclocking
architectureisshowninFigure4-1.
Table4-1.SystemClockModesandFixedRatiosforCoreClockDomains
SubsystemCoreClockDomainFixedRatiovs.DSPfrequency
DSPCLKDIV11:1
EDMACLKDIV31:3
VPSS
Peripherals(CLKDIV3domain)CLKDIV31:3
Peripherals(CLKDIV6domain)CLKDIV61:6
ThecoredomainsrefertotheclockdomainsforalloftheinternalprocessingelementsoftheDM643x
DMP,suchastheDSP/EDMA/peripherals,etc.AllinternalcommunicationsbetweenDSPandmodules
operateatcoredomainclockfrequencies.Allofthecoreclockdomainsaresynchronoustoeachother,
comefromasinglePLL(PLL1),havealignedclockedges,andhavefixeddividebyratiorequirements,as
showninTable4-1andFigure4-1.Itisuser'sresponsibilitytoensurethefixeddivideratiosbetween
thesecoreclockdomainsareachieved.
TheDSPisintheCLKDIV1domainandreceivesthePLL1frequencydirectly(PLLDIV1ofPLLcontroller
1(PLLC1)settodivideby1),orreceivesthedivided-downPLL1frequency(PLLDIV1ofPLLC1setto
divideby2,3,etc.).TheDSPhasinternalclockdividersthatitusestocreatetheDSP÷3clockfrequency
tocommunicatewithothercomponentson-chip.
ModulesintheCLKDIV3domain(forexample,EDMA,VPSS,CLKDIV3domainperipherals)mustrunat
1/3theDSPfrequency.
ModulesintheCLKDIV6domain(forexample,CLKDIV6domainperipherals)mustrunat1/6theDSP
frequency.
ModulesintheCLKINdomain(forexample,UART,Timer,I2C,PWM,HECC)runattheMXI/CLKIN
frequency,asynchronoustotheDSP.Thereisnofixedratiorequirementbetweentheseperipherals
frequenciesandtheDSPfrequency.
Refertodevice-specificdatamanualforthecoreclockdomainforeachperipheral.
30DeviceClockingSPRU978E–March2008
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