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5.3PLL2Control
PLLDIV2 (/10)
PLLDIV1 (/2)
1
0
PLLM
PLL
0
1
BPDIV
CLKMODE
CLKIN
OSCIN
PLLEN
PLL2_SYSCLK2
(VPSS−VPBE)
PLL2_SYSCLK1
(DDR2 PHY)
PLL2_SYSCLKBP
(DDR2 VTP)
PLLOUT
5.3.1DeviceClockGeneration
PLL2Control
PLL2providestheclockfromwhichtheDDR2memorycontrollerandoptionalVPBEclocksarederived.
TheDDRPLLcontroller2(PLLC2)controlsPLL2,whichacceptstheclockfromtheoscillatorandalso
generatesthevariousfrequencyclocksneeded.Figure5-2showsthecustomizationofPLL2inthe
DM643xDMP.ThePLL2clocksaredistributedtothedeviceasfollows:
•SYSCLK1:DDR2PHY
•SYSCLK2:VPSS
•SYSCLKBP:DDR2VTP
PLL2suppliestheDDR2memorycontrollerclock.SoftwarecontrolsthePLL2operationthroughtheDDR
PLLcontroller2(PLLC2)registers.TheregistersusedinPLLC2arelistedinSection5.4.ThePLL2
multiplieriscontrolledbythePLLMbitofthePLLmultipliercontrolregister(PLLM).ThePLL2multiplier
maybemodifiedbysoftware(forexample,totunetheDDRinterfaceforbestperformance).
ThePLL2outputclockmustbedivided-downtotheDDRoperatingrangeusingtheSYSCLK1divider.
Atpower-up,PLL2ispowered-downanddisabled,andmustbepowered-upbysoftwarethroughthePLL2
PLLPWRDNbitinthePLLcontrolregister(PLLCTL).Bydefault,thesystemoperatesinbypassmodeand
theDDRclockisprovideddirectlyfromtheinputreferenceclock.OncethePLLispowered-upandlocked,
softwarecanswitchthedevicetoPLLmodeoperationbysettingthePLLENbitinPLLCTLto1.
Figure5-2.PLL2StructureintheTMS320DM643xDMP
PLLC2generatestwoclocksfromthePLL2outputclockforusebytheDDR2memorycontrollerand
VPSSmodules.ThesearesummarizedinTable5-2.
Table5-2.DDRPLLC2OutputClocks
OutputClockUsedbyDefaultDivider
SYSCLK2VPSS/10
SYSCLK1DDRPhy/2
SYSCLKBPDDRVTPController/2
TheSYSCLK1outputclockdividervaluedefaultsto/2.Assuminga27MHZMXI/CLKINandthePLL2
defaultmultiplierof×20,thisresultsina270MHZDDRPhyclock(135MHZDDR2).Itcanbemodifiedby
software(RATIObitinPLLDIV1)incombinationwithotherPLLmultiplierstoachievethedesiredDDR
clockrate.TheSYSCLK2dividerisprogrammabletoallowa54MHZoutputtobegeneratedfromany
even-multiplePLLoutputfrequencyforusebytheVPSS.
SPRU978E–March2008PLLController43
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