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ClockDomains
Table4-6.PossibleClockingModes
VPSS_CLKCTL.MUXSELBitClockingModeDescription
0MXImodeBoththeVENCandtheDACgettheirclockfromPLLC1SYSCLKBP,which
defaultstotheMXI27MHZcrystalinputdivideby1.
1hPLL2modeThePLL2(divided-down)generatesa54MHZclock.BoththeDACandthe
VENCreceivethe54MHZ.TheVENCcanoptionallydivideitby2tocreatea
27MHZclock.NotethismoderequirestheDDR2clocksetting(fromPLL2)to
beanevenmultipleof27MHZsothatanintegerdivisorcanbeusedto
createthe54MHZDACclock.Thus,thismodelimitstheavailableDDR2
clockfrequencies.
2hVPBECLKmodeBoththeDACandtheVENCreceivetheVPBECLK.TheVENChasthe
optionofdividingitby2forprogressivescansupportdrivingin54MHZon
VPBECLK.
3hPCLKmodeTheVENCreceivesthePCLK.TheDACreceivesnoclock,andshouldbe
disabled.PCLKcanbeinvertedfornegativeedgesupport,selectablebya
memory-mappedregisterbit.
DeviceClocking 36SPRU978E–March2008
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