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5.3.2.2InitializationtoPLLModefromPLLPowerDown
PLL2Control
IfthePLLispowereddown(PLLPWRDNbitinPLLCTLissetto1),youmustfollowtheprocedurebelow
tochangePLL2frequencies.
1.SelecttheclockmodebyprogrammingtheCLKMODEbitinPLLCTL.
2.BeforechangingthePLLfrequency,switchtoPLLbypassmode:
a.ClearthePLLENSRCbitinPLLCTLto0toallowPLLCTL.PLLENtotakeeffect.
b.ClearthePLLENbitinPLLCTLto0(selectPLLbypassmode).
c.Waitfor4MXIcyclestoensurePLLCswitchestobypassmodeproperly.
3.ClearthePLLRSTbitinPLLCTLto0(resetPLL)
4.SetthePLLDISbitinPLLCTLto1(disablePLLoutput).
5.ClearthePLLPWRDNbitinPLLCTLto0tobringthePLLoutofpower-downmode.
6.ClearthePLLDISbitinPLLCTLto0(enablethePLL)toallowPLLoutputstostarttoggling.Notethat
thePLLCisstillatPLLbypassmode;therefore,thetogglingPLLoutputdoesnotgetpropagatedto
therestofthedevice.
7.WaitforPLLstabilizationtime.Seethedevice-specificdatamanualforPLLstabilizationtime.
8.ProgramtherequiredmultipliervalueinPLLM.
9.Ifnecessary,programPLLDIV1andPLLDIV2registerstochangetheSYSCLK1andSYSCLK2divide
values:
a.CheckfortheGOSTATbitinPLLSTATtoclearto0toindicatethatnoGOoperationiscurrentlyin
progress.
b.ProgramtheRATIOfieldinPLLDIV1andPLLDIV2withthedesireddividefactors.ForPLLC2,
thereisnospecificfrequencyratiorequirementsbetweenSYSCLK1andSYSCLK2.Makesurein
thisstepyouleavethePLLDIV1.D1ENandPLLDIV2.D2ENbitsset(default).
c.SettheGOSETbitinPLLCMDto1toinitiateanewdividertransition.Duringthistransition,
SYSCLK1andSYSCLK2arepausedmomentarily.
d.WaitforNnumberofPLLDIVnsourceclockcyclestoensuredividerchangeshavecompleted.See
Section5.3.2.4fortheformulaoncalculatingthenumberofcyclesN.
e.WaitfortheGOSTATbitinPLLSTATtoclearto0.
10.WaitforPLLtoresetproperly.Seethedevice-specificdatamanualforPLLresettime.
11.SetthePLLRSTbitinPLLCTLto1tobringthePLLoutofreset.
12.WaitforPLLtolock.Seethedevice-specificdatamanualforPLLlocktime.
13.SetthePLLENbitinPLLCTLto1toremovethePLLfrombypassmode.
ForinformationoninitializingtheDDR2memorycontroller,seetheTMS320DM643xDMPDDR2Memory
ControllerUser'sGuide(SPRU986).
SPRU978E–March2008PLLController45
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