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4.2.2CoreFrequencyFlexibility
ClockDomains
ThecorefrequencydomainclocksaresuppliedbythePLLcontroller1(PLLC1).Thesedomainclocksare
flexible,toadegree,withinthelimitationsspecifiedinthedevice-specificdatamanual.Allofthefollowing
frequencyrangesandmultiplier/dividerratiosinthedatamanualmustbeadheredto:
•Inputclockfrequencyrange(MXI/CLKIN)
•PLL1multiplier(PLLM)range
•PLL1output(PLLOUT)frequencyrangebasedonthecorevoltage(1.05Vor1.2V)ofthedevice
•Maximumdevicespeed
•PLLC1'sSYSCLK3:SYSCLK2:SYSCLK1frequencyratiomustbefixedto1:3:6.Forexample,if
SYSCLK1isat600MHZ,SYSCLK2mustbeat200MHZ,andSYSCLK3mustbeat100MHZ.
Asspecifiedinthedatamanual,thePLLscanbedrivenbyanyinputrangingfrom20to30MHZ.
However,a27MHZinputisrequiredifthevideoprocessingbackend(VPBE)subsystemisneededto
drivetelevisiondisplayswiththeintegratedvideoDACs.
Table4-2showssomeexamplePLL1multiplieranddividersettingsassumingMXI/CLKINfrequencyof27
MHZ.TheApplicabletoDeviceCoreVoltagecolumnindicateswhetherthesettingisallowedforagiven
devicecorevoltage.Forexample,thelastrowinTable4-2(PLL1multiplier22fora27MHZclockinput)
onlyappliestodeviceswithacorevoltage1.2VtomeetthePLL1output(PLLOUT)frequencyrange
requiredinthedatamanual.Inaddition,youmustensuretheSYSCLK1frequencydoesnotexceedthe
speedgradeofthedevice.Forexample,foradeviceratedat400MHZspeedgrade,SYSCLK1mustnot
exceed400MHZ.
Table4-2.ExamplePLL1FrequenciesandDividers(27MHZClockInput)
CLKDIV1DomainCLKDIV3DomainCLKDIV6DomainApplicabletoDevice
(SYSCLK1)(SYSCLK2)(SYSCLK3)CoreVoltage
PLL1
PLL1PLLOUTFreqFreqFreq
MultiplierFreq(MHZ)Divider
(1)
(MHZ)Divider
(1)
(MHZ)Divider
(1)
(MHZ)1.2V1.05V
15405.01405.03135.0667.5YY
16432.01432.03144.0672.0YY
17459.01459.03153.0676.5YY
18486.01486.03162.0681.0YY
19513.01513.03171.0685.5YY
20540.01540.03180.0690.0Y-
21567.01567.03189.0694.5Y-
22594.01594.03198.0699.0Y-
22594.02297.0699.01249.5Y-
(1)
TheRATIObitinPLLDIVnisprogrammedasDivider-1.Forexample,foraSYSCLK1dividerof1,youshouldprogram
PLLDIV1.RATIO=0,PLLDIV2.RATIO=2,PLLDIV3.RATIO=5.
32DeviceClockingSPRU978E–March2008
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