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4.2.3DDR2/EMIFClock
ClockDomains
TheDDR2interfacehasadedicatedclockdrivenfromPLL2.Thisisaseparateclocksystemfromthe
PLL1clocksprovidedtoothercomponentsofthesystem.Thisdedicatedclockallowsthereductionofthe
coreclockratestosavepowerwhilemaintainingtherequiredminimumclockrate(125MHZ)forDDR2.
PLL2mustbeconfiguredtooutputa2×clocktotheDDR2PHYinterface.
TheDM643xDMPvideoDACsarecapableofdrivinghighqualityprogressivetelevisiondisplays,ifdriven
bya54MHZinputclocksourcedbyPLL2(seetheTMS320DM643xDMPVideoProcessingBackEnd
(VPBE)User'sGuide(SPRU952)formoredetailedinformation).ThiswilllimitthepossiblePLL2settings
toamultipleof54MHZsothattheVPBEclockcanbederivedwithasimpleintegerclockdivider.
Allofthefollowingfrequencyrangesandmultiplier/dividerratiosinthedevice-specificdatamanualmust
beadheredtowhenconfiguringPLL2:
•Inputclockfrequencyrange(MXI/CLKIN)
•PLL2multiplier(PLLM)range
•PLL2output(PLLOUT)frequencyrangebasedoncorevoltage(1.05Vor1.2V)ofthedevice
Table4-3andTable4-4showsomePLL2/DDR2clockratesassumingaMXI/CLKINfrequencyof27
MHZ.Thesetablesalsoindicatesettingsthataremultiplesof54MHZ.
Table4-3.ExamplePLL2Frequencies(CoreVoltage=1.2V)
PLL2PLLOUTFreqSYSCLK1PHY[2×clock]
PLL2Multiplier(MHZ)Divider
(1)
(MHZ)DDR2Clock(MHZ)54MHZMultiple
28756.03252.0126.0Yes
19513.02256.5128.3No
29783.03261.0130.5No
20540.02270.0135.0Yes
31837.03279.0139.5No
21567.02283.5141.8No
32864.03288.0144.0Yes
22594.02297.0148.5Yes
23621.02310.5155.3No
24648.02324.0162.0Yes
25675.02337.5168.8No
(1)
TheRATIObitinPLLDIVnisprogrammedasDivider-1.Forexample,forSYSCLK1dividerof3,youshouldprogram
PLLDIV1.RATIO=2.
Table4-4.ExamplePLL2Frequencies(CoreVoltage=1.05V)
PLL2PLLOUTFreqSYSCLK1PHY[2×clock]
PLL2Multiplier(MHZ)Divider
(1)
(MHZ)DDR2Clock(MHZ)54MHZMultiple
19513.02256.5128.3No
20540.02270.0135.0Yes
21567.02283.5141.8No
22594.02297.0148.5Yes
23621.02310.5155.3No
24648.02324.0162.0Yes
(1)
TheRATIObitinPLLDIVnisprogrammedasDivider-1.Forexample,forSYSCLK1dividerof3,youshouldprogram
PLLDIV1.RATIO=2.
SPRU978E–March2008DeviceClocking33
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