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5.4.6PLLControllerDivider2Register(PLLDIV2)
5.4.7PLLControllerDivider3Register(PLLDIV3)
PLLControllerRegisters
ThePLLcontrollerdivider2register(PLLDIV2)isshowninFigure5-8anddescribedinTable5-10.
Divider2controlsdividerforSYSCLK2.
Figure5-8.PLLControllerDivider2Register(PLLDIV2)
3116
Reserved
R-0
1514540
D2ENReservedRATIO
R/W-1R-0R/W-2hor9h
(1)
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
(1)
ForPLLC1,RATIOdefaultsto2h(PLL1divideby3);forPLLC2,RATIOdefaultsto9h(PLL2divideby10).
Table5-10.PLLControllerDivider2Register(PLLDIV2)FieldDescriptions
BitFieldValueDescription
31-16Reserved0Reserved
15D2ENDivider2enable.
0Divider2isdisabled.
1Divider2isenabled.
14-5Reserved0Reserved
4-0RATIO0-1FhDividerratio.Dividervalue=RATIO+1.Forexample,RATIO=0meansdivideby1.
ThePLLcontrollerdivider3register(PLLDIV3)isshowninFigure5-9anddescribedinTable5-11.
Divider3controlsdividerforSYSCLK3.PLLDIV3isnotusedonPLLC2.
Figure5-9.PLLControllerDivider3Register(PLLDIV3)
3116
Reserved
R-0
1514540
D3ENReservedRATIO
R/W-1R-0R/W-5h
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table5-11.PLLControllerDivider3Register(PLLDIV3)FieldDescriptions
BitFieldValueDescription
31-16Reserved0Reserved
15D3ENDivider3enable.
0Divider3isdisabled.
1Divider3isenabled.
14-5Reserved0Reserved
4-0RATIO0-1FhDividerratio.Dividervalue=RATIO+1.Forexample,RATIO=0meansdivideby1.
PLLController 52SPRU978E–March2008
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