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5.2.2.3ChangingSYSCLKDividers
PLL1Control
ThissectiondiscussesthesoftwaresequencetochangetheSYSCLKdividers.TheSYSCLKdivider
changesequenceisalsoreferredtoasGOoperation,asitinvolveshittingtheGObit(GOSETbitin
PLLCMD)toinitiatethedividerchange.Therecommendationistostopallperipheraloperationbefore
changingtheSYSCLKdividers,withtheexceptionoftheC64x+DSPandDDR2.TheC64x+DSPmust
beoperationaltoprogramthePLLcontroller.DDR2operatesoffoftheclockfromPLLC2.
1.CheckfortheGOSTATbitinPLLSTATtoclearto0toindicatethatnoGOoperationiscurrentlyin
progress.
2.ProgramtheRATIOfieldinPLLDIV1,PLLDIV2,andPLLDIV3withthedesireddividefactors.Notethat
thedividersmustmaintaina1:3:6ratiotosatisfytheCLKDIV1,CLKDIV3,CLKDIV6clockdomain
requirements.Seethedevice-specificdatamanualformoredetailsonClockDomains.Inaddition,
makesureinthisstepyouleavethePLLDIV1.D1EN,PLLDIV2.D2EN,andPLLDIV3.D3ENbitsset
(default).
3.SettheGOSETbitinPLLCMDto1toinitiateanewdividertransition.Duringthistransition,SYSCLK1,
SYSCLK2,andSYSCLK3arepausedmomentarily.
4.WaitforNnumberofPLLDIVnsourceclockcyclestoensuredividerchangeshavecompleted.Seethe
followingformulaforcalculatingthenumberofcyclesN.
5.WaitfortheGOSTATbitinPLLSTATtoclearto0.
ThefollowingformulashouldbeusedtocalculatethenumberofPLLDIVnsourceclockcycles:
N=(2×LeastCommonMultiple[LCM]ofalltheoldSYSCLKdividevalues)+50cyclesoverhead
Example5-1.CalculatingNumberofClockCyclesN
ThisexamplecalculatesthenumberofclockcyclesN.
•Settingsbeforedividerchange:
–PLLDIV1.RATIO=0(divide-by-1)
–PLLDIV2.RATIO=2(divide-by-3)
–PLLDIV3.RATIO=5(divide-by-6)
•Newdividersettings:
–PLLDIV1.RATIO=1(divide-by-2)
–PLLDIV2.RATIO=5(divide-by-6)
–PLLDIV3.RATIO=11(divide-by-12)
Theleastcommonmultiplebetweentheolddividervaluesof/1,/3,and/6is/6;therefore,thenumber
ofcyclesNis:
N=(2×6)+50cyclesoverhead=62PLLDIVnsourceclockcycles
IfPLLC1isinPLLmode(PLLCTL.PLLEN=1),thePLLDIVnsourceclockisthePLL1outputclock.If
PLLC1isinPLLbypassmode(PLLCTL.PLLEN=0),thePLLDIVnsourceclockisthedeviceclock
sourceMXI/CLKIN.
42PLLControllerSPRU978E–March2008
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