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3.1MemoryMap
3.1.1DSPInternalMemory(L1P,L1D,L2)
3.1.2ExternalMemory
3.1.3InternalPeripherals
3.1.4DevicePeripherals
MemoryMap
Refertoyourdevice-specificdatamanualformemory-mapinformation.
ThissectiondescribestheconfigurationoftheDSPinternalmemoryintheDM643xDMPthatconsistsof
L1P,L1D,andL2.IntheDM643xDMP:
•L1Pmemory:TheL1PcontrollerallowsyoutoconfigurepartoralloftheL1PRAMasnormalprogram
RAMorasdirectmappedcache.Youcanconfigurecachesizesof0KB,4KB,8KB,16KB,or32KB
oftheRAM.
•L1Dmemory:TheL1DcontrollerallowsyoutoconfigurepartoftheL1DRAMasnormaldataRAMor
ascache.Youcanconfigurecachesizesof0KB,4KB,8KB,16KB,or32KBoftheRAM.
•L2memory:TheL2controllerallowsyoutoconfigurepartoralloftheL2RAMasnormalRAMoras
cache.Youcanconfigurecachesizesof0KB,32KB,64KB,or128KBoftheRAM.
Refertodevice-specificdatamanualfortheexactamountofRAM/cache.RefertoTMS320C64x+DSP
MegamoduleReferenceGuide(SPRU871)forinformationonhowtoconfigurethecache.
TheDSPhasaccesstothefollowingexternalmemories:
•DDR2synchronousDRAM
•AsynchronousEMIF/NOR/NANDFlash
Theexternalmemorycontroller(EMC)facilitatesDSPaccesstothesememoriesintheC64x+
Megamodule.ThefollowingexternalmemoriesareaccessibletotheDSP:
•DDR2port
•AsynchronousEMIF(forexample,NORandNANDFlashin4EM_CSregions)
Forthememory-maplocationsoftheseexternalmemories,refertothememory-mapsectionofthe
device-specificdatamanual.
ThefollowinginternalperipheralsareaccessibletotheDSP:
•Power-downcontroller(PDC)
•Interruptcontroller(INTC)
Formoreinformationontheinternalperipherals,seetheTMS320C64x+DSPMegamoduleReference
Guide(SPRU871).
TheDSPhasaccesstoallperipheralsonthedevice.Refertodevice-specificdatamanualforthefulllist
ofperipherals.
SystemMemory 26SPRU978E–March2008
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