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Contents
Preface...............................................................................................................................9
1Introduction.............................................................................................................11
1.1Introduction.........................................................................................................12
1.2BlockDiagram.....................................................................................................12
1.3DSPSubsysteminTMS320DM643xDMP....................................................................13
1.3.1ComponentsoftheDSPSubsystem..................................................................13
2TMS320C64x+Megamodule.......................................................................................15
2.1Introduction.........................................................................................................16
2.2TMS320C64x+CPU..............................................................................................16
2.3MemoryControllers...............................................................................................18
2.3.1L1PController............................................................................................18
2.3.2L1DController............................................................................................20
2.3.3L2Controller..............................................................................................20
2.3.4ExternalMemoryController(EMC)....................................................................21
2.3.5InternalDMA(IDMA).....................................................................................21
2.4InternalPeripherals...............................................................................................22
2.4.1InterruptController(INTC)..............................................................................22
2.4.2Power-DownController(PDC)..........................................................................22
2.4.3BandwidthManager......................................................................................23
3SystemMemory.......................................................................................................25
3.1MemoryMap.......................................................................................................26
3.1.1DSPInternalMemory(L1P,L1D,L2).................................................................26
3.1.2ExternalMemory.........................................................................................26
3.1.3InternalPeripherals......................................................................................26
3.1.4DevicePeripherals.......................................................................................26
3.2MemoryInterfacesOverview....................................................................................27
3.2.1DDR2ExternalMemoryInterface......................................................................27
3.2.2ExternalMemoryInterface..............................................................................27
4DeviceClocking.......................................................................................................29
4.1Overview............................................................................................................30
4.2ClockDomains.....................................................................................................30
4.2.1CoreDomains............................................................................................30
4.2.2CoreFrequencyFlexibility..............................................................................32
4.2.3DDR2/EMIFClock........................................................................................33
4.2.4I/ODomains...............................................................................................34
4.2.5VideoProcessingBackEnd............................................................................35
5PLLController..........................................................................................................37
5.1PLLModule........................................................................................................38
5.2PLL1Control.......................................................................................................38
5.2.1DeviceClockGeneration................................................................................39
5.2.2StepsforChangingPLL1/CoreDomainFrequency.................................................39
5.3PLL2Control.......................................................................................................43
5.3.1DeviceClockGeneration................................................................................43
SPRU978E–March2008Contents3
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