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Preface
SPRU978E–March2008
ReadThisFirst
AboutThisManual
ThisdocumentdescribestheDSPsubsystemintheTMS320DM643xDigitalMediaProcessor(DMP).
NotationalConventions
Thisdocumentusesthefollowingconventions.
•Hexadecimalnumbersareshownwiththesuffixh.Forexample,thefollowingnumberis40
hexadecimal(decimal64):40h.
•Registersinthisdocumentareshowninfiguresanddescribedintables.
–Eachregisterfigureshowsarectangledividedintofieldsthatrepresentthefieldsoftheregister.
Eachfieldislabeledwithitsbitname,itsbeginningandendingbitnumbersabove,andits
read/writepropertiesbelow.Alegendexplainsthenotationusedfortheproperties.
–Reservedbitsinaregisterfiguredesignateabitthatisusedforfuturedeviceexpansion.
RelatedDocumentationFromTexasInstruments
ThefollowingdocumentsdescribetheTMS320DM643xDigitalMediaProcessor(DMP).Copiesofthese
documentsareavailableontheInternetatwww.ti.com.Tip:Entertheliteraturenumberinthesearchbox
providedatwww.ti.com.
ThecurrentdocumentationthatdescribestheDM643xDMP,relatedperipherals,andothertechnical
collateral,isavailableintheC6000DSPproductfolderat:www.ti.com/c6000.
SPRU983—TMS320DM643xDMPPeripheralsOverviewReferenceGuide.Providesanoverviewand
brieflydescribestheperipheralsavailableontheTMS320DM643xDigitalMediaProcessor(DMP).
SPRAA84—TMS320C64xtoTMS320C64x+CPUMigrationGuide.Describesmigratingfromthe
TexasInstrumentsTMS320C64xdigitalsignalprocessor(DSP)totheTMS320C64x+DSP.The
objectiveofthisdocumentistoindicatedifferencesbetweenthetwocores.Functionalityinthe
devicesthatisidenticalisnotincluded.
SPRU732—TMS320C64x/C64x+DSPCPUandInstructionSetReferenceGuide.DescribestheCPU
architecture,pipeline,instructionset,andinterruptsfortheTMS320C64xandTMS320C64x+digital
signalprocessors(DSPs)oftheTMS320C6000DSPfamily.TheC64x/C64x+DSPgeneration
comprisesfixed-pointdevicesintheC6000DSPplatform.TheC64x+DSPisanenhancementof
theC64xDSPwithaddedfunctionalityandanexpandedinstructionset.
SPRU871—TMS320C64x+DSPMegamoduleReferenceGuide.DescribestheTMS320C64x+digital
signalprocessor(DSP)megamodule.Includedisadiscussionontheinternaldirectmemoryaccess
(IDMA)controller,theinterruptcontroller,thepower-downcontroller,memoryprotection,bandwidth
management,andthememoryandcache.
SPRU862—TMS320C64x+DSPCacheUser'sGuide.Explainsthefundamentalsofmemorycaches
anddescribeshowthetwo-levelcache-basedinternalmemoryarchitectureintheTMS320C64x+
digitalsignalprocessor(DSP)oftheTMS320C6000DSPfamilycanbeefficientlyusedinDSP
applications.Showshowtomaintaincoherencewithexternalmemory,howtouseDMAtoreduce
memorylatencies,andhowtooptimizeyourcodetoimprovecacheefficiency.Theinternalmemory
architectureintheC64x+DSPisorganizedinatwo-levelhierarchyconsistingofadedicated
programcache(L1P)andadedicateddatacache(L1D)onthefirstlevel.AccessesbytheCPUto
thethesefirstlevelcachescancompletewithoutCPUpipelinestalls.Ifthedatarequestedbythe
CPUisnotcontainedincache,itisfetchedfromthenextlowermemorylevel,L2orexternal
memory.
SPRU978E–March2008ReadThisFirst9
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