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2.3.2L1DController
2.3.3L2Controller
MemoryControllers
TheL1Dcontrolleristhehardwareinterfacebetweenlevel1datamemory(L1Dmemory)andtheother
componentsintheC64x+Megamodule(forexample,C64x+CPU,L2controller,andEMC).TheL1D
controllerrespondstodatarequestsfromtheC64x+CPUandmanagestransferoperationsbetweenL1D
memoryandtheL2controllerandbetweenL1DmemoryandtheEMC.
Refertothedevice-specificdatamanualfortheamountofL1Dmemoryonthedevice.TheL1Dcontroller
hasaregisterinterfacethatallowsyoutoconfigurepartoftheL1DRAMasnormaldataRAMoras
cache.Youcanconfigurecachesizesof0KB,4KB,8KB,16KB,or32KBoftheRAM.
TheL1Disdividedintotworegions—denotedL1Dregion0andL1Dregion1.ThisistheL1Darchitecture
ontheDM643xDMP:
•L1Dregion0:OnsomeDM643xdevices,thisregionispopulatedwithmappedmemory.Ifitis
populatedwithmemory,thisregionisshownas“L1DRAM”inthedevice-specificdatamanual.
•L1Dregion1:Populatedwithmemorythatcanbeconfiguredasmappedmemoryorcache.This
regionisshownas“L1DRAM/Cache”inthedevice-specificdatamanual.
TheDM643xDMPdoesnotsupporttheL1Dmemoryprotectionfeaturesofthestandard
C64x+Megamodule.
RefertotheTMS320C64x+DSPCacheUser’sGuide(SPRU862)andtotheL1Dcontrollersectionofthe
TMS320C64x+DSPMegamoduleReferenceGuide(SPRU871)formoreinformationontheL1Dcontroller
andforadescriptionofitscontrolregisters.
TheL2controlleristhehardwareinterfacebetweenlevel2memory(L2memory)andtheother
componentsintheC64x+Megamodule(forexample,L1Pcontroller,L1Dcontroller,andEMC).TheL2
controllermanagestransferoperationsbetweenL2memoryandtheothermemorycontrollers(L1P
controller,L1Dcontroller,andEMC).
Refertodevice-specificdatamanualfortheamountofL2memoryonthedevice.TheL2controllerhasa
registerinterfacethatallowsyoutoconfigurepartoralloftheL2RAMasnormalRAMorascache.You
canconfigurecachesizesof0KB,32KB,64KB,or128KBoftheRAM.
TheL2memoryimplementstwoseparatememoryports.ThisistheL2architectureontheDM643xDMP:
•Port0
–Shownas“L2RAM/Cache”inthedevice-specificdatamanual.
–Bankingscheme:2×128-bitbanks
–Latency:1cycle(0waitstate)
•Port1
–Shownas“BootROM”inthedevice-specificdatamanual.
–Bankingscheme:1×256-bitbank
–Latency:1cycle(0waitstate)
TheDM643xDMPdoesnotsupporttheL2memoryprotectionfeatureofthestandard
C64x+Megamodule.
RefertotheTMS320C64x+DSPCacheUser’sGuide(SPRU862)andtotheL2controllersectionofthe
TMS320C64x+DSPMegamoduleReferenceGuide(SPRU871)formoreinformationontheL2controller
andforadescriptionofitscontrolregisters.
TMS320C64x+Megamodule 20SPRU978E–March2008
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